mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-05 10:04:12 +08:00
911c29b0e5
To insert the code for power on/off with pmu control to support hotplug in/out core1 As for hotplug.c, the codes for core1 to be hotplug in/out is inserted. As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined. As for platsmp.c, the codes for core1 to be powered on is inserted. Signed-off-by: JungHi Min <junghi.min@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
229 lines
5.5 KiB
C
229 lines
5.5 KiB
C
/* linux/arch/arm/mach-exynos4/platsmp.c
|
|
*
|
|
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
|
|
*
|
|
* Copyright (C) 2002 ARM Ltd.
|
|
* All Rights Reserved
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/device.h>
|
|
#include <linux/jiffies.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/hardware/gic.h>
|
|
#include <asm/smp_scu.h>
|
|
#include <asm/unified.h>
|
|
|
|
#include <mach/hardware.h>
|
|
#include <mach/regs-clock.h>
|
|
#include <mach/regs-pmu.h>
|
|
|
|
extern void exynos4_secondary_startup(void);
|
|
|
|
#define CPU1_BOOT_REG S5P_VA_SYSRAM
|
|
|
|
/*
|
|
* control for which core is the next to come out of the secondary
|
|
* boot "holding pen"
|
|
*/
|
|
|
|
volatile int __cpuinitdata pen_release = -1;
|
|
|
|
/*
|
|
* Write pen_release in a way that is guaranteed to be visible to all
|
|
* observers, irrespective of whether they're taking part in coherency
|
|
* or not. This is necessary for the hotplug code to work reliably.
|
|
*/
|
|
static void write_pen_release(int val)
|
|
{
|
|
pen_release = val;
|
|
smp_wmb();
|
|
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
|
|
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
|
|
}
|
|
|
|
static void __iomem *scu_base_addr(void)
|
|
{
|
|
return (void __iomem *)(S5P_VA_SCU);
|
|
}
|
|
|
|
static DEFINE_SPINLOCK(boot_lock);
|
|
|
|
static void __cpuinit exynos4_gic_secondary_init(void)
|
|
{
|
|
void __iomem *dist_base = S5P_VA_GIC_DIST +
|
|
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
|
|
void __iomem *cpu_base = S5P_VA_GIC_CPU +
|
|
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
|
|
int i;
|
|
|
|
/*
|
|
* Deal with the banked PPI and SGI interrupts - disable all
|
|
* PPI interrupts, ensure all SGI interrupts are enabled.
|
|
*/
|
|
__raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
|
|
__raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
|
|
|
|
/*
|
|
* Set priority on PPI and SGI interrupts
|
|
*/
|
|
for (i = 0; i < 32; i += 4)
|
|
__raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
|
|
|
|
__raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
|
|
__raw_writel(1, cpu_base + GIC_CPU_CTRL);
|
|
}
|
|
|
|
void __cpuinit platform_secondary_init(unsigned int cpu)
|
|
{
|
|
/*
|
|
* if any interrupts are already enabled for the primary
|
|
* core (e.g. timer irq), then they will not have been enabled
|
|
* for us: do so
|
|
*/
|
|
exynos4_gic_secondary_init();
|
|
|
|
/*
|
|
* let the primary processor know we're out of the
|
|
* pen, then head off into the C entry point
|
|
*/
|
|
write_pen_release(-1);
|
|
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
spin_lock(&boot_lock);
|
|
spin_unlock(&boot_lock);
|
|
}
|
|
|
|
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
{
|
|
unsigned long timeout;
|
|
|
|
/*
|
|
* Set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
* the holding pen - release it, then wait for it to flag
|
|
* that it has been released by resetting pen_release.
|
|
*
|
|
* Note that "pen_release" is the hardware CPU ID, whereas
|
|
* "cpu" is Linux's internal ID.
|
|
*/
|
|
write_pen_release(cpu);
|
|
|
|
if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
|
|
__raw_writel(S5P_CORE_LOCAL_PWR_EN,
|
|
S5P_ARM_CORE1_CONFIGURATION);
|
|
|
|
timeout = 10;
|
|
|
|
/* wait max 10 ms until cpu1 is on */
|
|
while ((__raw_readl(S5P_ARM_CORE1_STATUS)
|
|
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
|
|
if (timeout-- == 0)
|
|
break;
|
|
|
|
mdelay(1);
|
|
}
|
|
|
|
if (timeout == 0) {
|
|
printk(KERN_ERR "cpu1 power enable failed");
|
|
spin_unlock(&boot_lock);
|
|
return -ETIMEDOUT;
|
|
}
|
|
}
|
|
/*
|
|
* Send the secondary CPU a soft interrupt, thereby causing
|
|
* the boot monitor to read the system wide flags register,
|
|
* and branch to the address found there.
|
|
*/
|
|
|
|
timeout = jiffies + (1 * HZ);
|
|
while (time_before(jiffies, timeout)) {
|
|
smp_rmb();
|
|
|
|
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
|
|
CPU1_BOOT_REG);
|
|
gic_raise_softirq(cpumask_of(cpu), 1);
|
|
|
|
if (pen_release == -1)
|
|
break;
|
|
|
|
udelay(10);
|
|
}
|
|
|
|
/*
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
|
|
/*
|
|
* Initialise the CPU possible map early - this describes the CPUs
|
|
* which may be present or become present in the system.
|
|
*/
|
|
|
|
void __init smp_init_cpus(void)
|
|
{
|
|
void __iomem *scu_base = scu_base_addr();
|
|
unsigned int i, ncores;
|
|
|
|
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
|
|
|
|
/* sanity check */
|
|
if (ncores > NR_CPUS) {
|
|
printk(KERN_WARNING
|
|
"EXYNOS4: no. of cores (%d) greater than configured "
|
|
"maximum of %d - clipping\n",
|
|
ncores, NR_CPUS);
|
|
ncores = NR_CPUS;
|
|
}
|
|
|
|
for (i = 0; i < ncores; i++)
|
|
set_cpu_possible(i, true);
|
|
|
|
set_smp_cross_call(gic_raise_softirq);
|
|
}
|
|
|
|
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Initialise the present map, which describes the set of CPUs
|
|
* actually populated at the present time.
|
|
*/
|
|
for (i = 0; i < max_cpus; i++)
|
|
set_cpu_present(i, true);
|
|
|
|
scu_enable(scu_base_addr());
|
|
|
|
/*
|
|
* Write the address of secondary startup into the
|
|
* system-wide flags register. The boot monitor waits
|
|
* until it receives a soft interrupt, and then the
|
|
* secondary CPU branches to this address.
|
|
*/
|
|
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
|
|
}
|