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a8769a594a
IRQ_MCT_L1 is connected directly to GIC in external GIC mapping, while in internal GIC mapping, it is connected to GIC through interrupt combiner. Therfore the affinity for mct1 event timer interrupt should be changed through IRQ_MCT_L1. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
422 lines
10 KiB
C
422 lines
10 KiB
C
/* linux/arch/arm/mach-exynos4/mct.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 MCT(Multi-Core Timer) support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/percpu.h>
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#include <mach/map.h>
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#include <mach/regs-mct.h>
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#include <asm/mach/time.h>
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static unsigned long clk_cnt_per_tick;
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static unsigned long clk_rate;
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struct mct_clock_event_device {
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struct clock_event_device *evt;
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void __iomem *base;
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};
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struct mct_clock_event_device mct_tick[2];
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static void exynos4_mct_write(unsigned int value, void *addr)
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{
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void __iomem *stat_addr;
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u32 mask;
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u32 i;
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__raw_writel(value, addr);
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switch ((u32) addr) {
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case (u32) EXYNOS4_MCT_G_TCON:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 16; /* G_TCON write status */
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break;
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case (u32) EXYNOS4_MCT_G_COMP0_L:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 0; /* G_COMP0_L write status */
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break;
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case (u32) EXYNOS4_MCT_G_COMP0_U:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 1; /* G_COMP0_U write status */
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break;
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case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
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stat_addr = EXYNOS4_MCT_G_WSTAT;
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mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
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break;
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case (u32) EXYNOS4_MCT_G_CNT_L:
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
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mask = 1 << 0; /* G_CNT_L write status */
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break;
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case (u32) EXYNOS4_MCT_G_CNT_U:
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stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
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mask = 1 << 1; /* G_CNT_U write status */
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break;
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case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
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stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 3; /* L0_TCON write status */
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break;
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case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
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stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 3; /* L1_TCON write status */
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break;
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case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
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stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 0; /* L0_TCNTB write status */
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break;
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case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
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stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 0; /* L1_TCNTB write status */
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break;
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case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
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stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 1; /* L0_ICNTB write status */
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break;
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case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
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stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
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mask = 1 << 1; /* L1_ICNTB write status */
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break;
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default:
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return;
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}
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/* Wait maximum 1 ms until written values are applied */
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for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
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if (__raw_readl(stat_addr) & mask) {
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__raw_writel(mask, stat_addr);
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return;
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}
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panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
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}
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/* Clocksource handling */
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static void exynos4_mct_frc_start(u32 hi, u32 lo)
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{
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u32 reg;
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exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
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exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
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reg = __raw_readl(EXYNOS4_MCT_G_TCON);
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reg |= MCT_G_TCON_START;
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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}
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static cycle_t exynos4_frc_read(struct clocksource *cs)
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{
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unsigned int lo, hi;
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u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
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do {
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hi = hi2;
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lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
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hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
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} while (hi != hi2);
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return ((cycle_t)hi << 32) | lo;
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}
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struct clocksource mct_frc = {
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.name = "mct-frc",
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.rating = 400,
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.read = exynos4_frc_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init exynos4_clocksource_init(void)
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{
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exynos4_mct_frc_start(0, 0);
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if (clocksource_register_hz(&mct_frc, clk_rate))
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panic("%s: can't register clocksource\n", mct_frc.name);
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}
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static void exynos4_mct_comp0_stop(void)
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{
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unsigned int tcon;
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tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
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tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
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exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
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exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
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}
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static void exynos4_mct_comp0_start(enum clock_event_mode mode,
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unsigned long cycles)
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{
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unsigned int tcon;
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cycle_t comp_cycle;
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tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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tcon |= MCT_G_TCON_COMP0_AUTO_INC;
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exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
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}
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comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
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exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
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exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
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exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
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tcon |= MCT_G_TCON_COMP0_ENABLE;
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exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
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}
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static int exynos4_comp_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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exynos4_mct_comp0_start(evt->mode, cycles);
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return 0;
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}
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static void exynos4_comp_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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exynos4_mct_comp0_stop();
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device mct_comp_device = {
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.name = "mct-comp",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 250,
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.set_next_event = exynos4_comp_set_next_event,
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.set_mode = exynos4_comp_set_mode,
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};
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static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction mct_comp_event_irq = {
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.name = "mct_comp_irq",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = exynos4_mct_comp_isr,
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.dev_id = &mct_comp_device,
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};
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static void exynos4_clockevent_init(void)
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{
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clk_cnt_per_tick = clk_rate / 2 / HZ;
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clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
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mct_comp_device.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &mct_comp_device);
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mct_comp_device.min_delta_ns =
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clockevent_delta2ns(0xf, &mct_comp_device);
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mct_comp_device.cpumask = cpumask_of(0);
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clockevents_register_device(&mct_comp_device);
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setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
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}
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#ifdef CONFIG_LOCAL_TIMERS
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/* Clock event handling */
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static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
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{
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unsigned long tmp;
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unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
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void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
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tmp = __raw_readl(addr);
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if (tmp & mask) {
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tmp &= ~mask;
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exynos4_mct_write(tmp, addr);
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}
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}
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static void exynos4_mct_tick_start(unsigned long cycles,
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struct mct_clock_event_device *mevt)
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{
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unsigned long tmp;
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exynos4_mct_tick_stop(mevt);
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tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
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/* update interrupt count buffer */
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exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
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/* enable MCT tick interrupt */
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
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tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
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tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
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MCT_L_TCON_INTERVAL_MODE;
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exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
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}
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static int exynos4_tick_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
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exynos4_mct_tick_start(cycles, mevt);
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return 0;
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}
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static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
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exynos4_mct_tick_stop(mevt);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
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{
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struct mct_clock_event_device *mevt = dev_id;
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struct clock_event_device *evt = mevt->evt;
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/*
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* This is for supporting oneshot mode.
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* Mct would generate interrupt periodically
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* without explicit stopping.
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*/
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if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
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exynos4_mct_tick_stop(mevt);
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/* Clear the MCT tick interrupt */
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exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction mct_tick0_event_irq = {
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.name = "mct_tick0_irq",
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.flags = IRQF_TIMER | IRQF_NOBALANCING,
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.handler = exynos4_mct_tick_isr,
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};
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static struct irqaction mct_tick1_event_irq = {
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.name = "mct_tick1_irq",
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.flags = IRQF_TIMER | IRQF_NOBALANCING,
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.handler = exynos4_mct_tick_isr,
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};
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static void exynos4_mct_tick_init(struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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mct_tick[cpu].evt = evt;
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if (cpu == 0) {
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mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
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evt->name = "mct_tick0";
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} else {
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mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
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evt->name = "mct_tick1";
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}
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evt->cpumask = cpumask_of(cpu);
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evt->set_next_event = exynos4_tick_set_next_event;
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evt->set_mode = exynos4_tick_set_mode;
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evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->rating = 450;
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clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
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evt->max_delta_ns =
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clockevent_delta2ns(0x7fffffff, evt);
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evt->min_delta_ns =
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clockevent_delta2ns(0xf, evt);
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clockevents_register_device(evt);
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exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
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if (cpu == 0) {
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mct_tick0_event_irq.dev_id = &mct_tick[cpu];
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setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
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} else {
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mct_tick1_event_irq.dev_id = &mct_tick[cpu];
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setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
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irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
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}
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}
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/* Setup the local clock events for a CPU */
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void __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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exynos4_mct_tick_init(evt);
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}
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int local_timer_ack(void)
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{
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return 0;
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}
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#endif /* CONFIG_LOCAL_TIMERS */
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static void __init exynos4_timer_resources(void)
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{
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struct clk *mct_clk;
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mct_clk = clk_get(NULL, "xtal");
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clk_rate = clk_get_rate(mct_clk);
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}
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static void __init exynos4_timer_init(void)
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{
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exynos4_timer_resources();
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exynos4_clocksource_init();
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exynos4_clockevent_init();
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}
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struct sys_timer exynos4_timer = {
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.init = exynos4_timer_init,
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};
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