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b0b6ff0b21
This patch includes the implementation of the clock gating for System MMU. Initially, all System MMUs are not asserted the system clock. Asserting the system clock to a System MMU is enabled only when s5p_sysmmu_enable() is called. Likewise, it is disabled only when s5p_sysmmu_disable() is called. Therefore, clock gating on System MMUs are still invisible to the outside of the System MMU driver. Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
233 lines
5.1 KiB
C
233 lines
5.1 KiB
C
/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - System MMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/sysmmu.h>
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#include <plat/s5p-clock.h>
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/* These names must be equal to the clock names in mach-exynos4/clock.c */
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const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
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"SYSMMU_MDMA" ,
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"SYSMMU_SSS" ,
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"SYSMMU_FIMC0" ,
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"SYSMMU_FIMC1" ,
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"SYSMMU_FIMC2" ,
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"SYSMMU_FIMC3" ,
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"SYSMMU_JPEG" ,
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"SYSMMU_FIMD0" ,
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"SYSMMU_FIMD1" ,
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"SYSMMU_PCIe" ,
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"SYSMMU_G2D" ,
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"SYSMMU_ROTATOR",
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"SYSMMU_MDMA2" ,
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"SYSMMU_TV" ,
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"SYSMMU_MFC_L" ,
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"SYSMMU_MFC_R" ,
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};
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static struct resource exynos4_sysmmu_resource[] = {
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[0] = {
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.start = EXYNOS4_PA_SYSMMU_MDMA,
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.end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_SYSMMU_MDMA0_0,
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.end = IRQ_SYSMMU_MDMA0_0,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = EXYNOS4_PA_SYSMMU_SSS,
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.end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[3] = {
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.start = IRQ_SYSMMU_SSS_0,
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.end = IRQ_SYSMMU_SSS_0,
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.flags = IORESOURCE_IRQ,
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},
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[4] = {
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.start = EXYNOS4_PA_SYSMMU_FIMC0,
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.end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[5] = {
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.start = IRQ_SYSMMU_FIMC0_0,
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.end = IRQ_SYSMMU_FIMC0_0,
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.flags = IORESOURCE_IRQ,
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},
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[6] = {
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.start = EXYNOS4_PA_SYSMMU_FIMC1,
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.end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[7] = {
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.start = IRQ_SYSMMU_FIMC1_0,
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.end = IRQ_SYSMMU_FIMC1_0,
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.flags = IORESOURCE_IRQ,
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},
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[8] = {
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.start = EXYNOS4_PA_SYSMMU_FIMC2,
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.end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[9] = {
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.start = IRQ_SYSMMU_FIMC2_0,
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.end = IRQ_SYSMMU_FIMC2_0,
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.flags = IORESOURCE_IRQ,
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},
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[10] = {
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.start = EXYNOS4_PA_SYSMMU_FIMC3,
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.end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[11] = {
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.start = IRQ_SYSMMU_FIMC3_0,
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.end = IRQ_SYSMMU_FIMC3_0,
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.flags = IORESOURCE_IRQ,
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},
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[12] = {
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.start = EXYNOS4_PA_SYSMMU_JPEG,
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.end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[13] = {
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.start = IRQ_SYSMMU_JPEG_0,
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.end = IRQ_SYSMMU_JPEG_0,
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.flags = IORESOURCE_IRQ,
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},
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[14] = {
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.start = EXYNOS4_PA_SYSMMU_FIMD0,
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.end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[15] = {
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.start = IRQ_SYSMMU_LCD0_M0_0,
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.end = IRQ_SYSMMU_LCD0_M0_0,
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.flags = IORESOURCE_IRQ,
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},
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[16] = {
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.start = EXYNOS4_PA_SYSMMU_FIMD1,
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.end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[17] = {
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.start = IRQ_SYSMMU_LCD1_M1_0,
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.end = IRQ_SYSMMU_LCD1_M1_0,
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.flags = IORESOURCE_IRQ,
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},
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[18] = {
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.start = EXYNOS4_PA_SYSMMU_PCIe,
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.end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[19] = {
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.start = IRQ_SYSMMU_PCIE_0,
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.end = IRQ_SYSMMU_PCIE_0,
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.flags = IORESOURCE_IRQ,
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},
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[20] = {
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.start = EXYNOS4_PA_SYSMMU_G2D,
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.end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[21] = {
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.start = IRQ_SYSMMU_2D_0,
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.end = IRQ_SYSMMU_2D_0,
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.flags = IORESOURCE_IRQ,
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},
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[22] = {
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.start = EXYNOS4_PA_SYSMMU_ROTATOR,
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.end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[23] = {
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.start = IRQ_SYSMMU_ROTATOR_0,
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.end = IRQ_SYSMMU_ROTATOR_0,
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.flags = IORESOURCE_IRQ,
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},
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[24] = {
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.start = EXYNOS4_PA_SYSMMU_MDMA2,
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.end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[25] = {
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.start = IRQ_SYSMMU_MDMA1_0,
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.end = IRQ_SYSMMU_MDMA1_0,
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.flags = IORESOURCE_IRQ,
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},
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[26] = {
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.start = EXYNOS4_PA_SYSMMU_TV,
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.end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[27] = {
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.start = IRQ_SYSMMU_TV_M0_0,
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.end = IRQ_SYSMMU_TV_M0_0,
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.flags = IORESOURCE_IRQ,
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},
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[28] = {
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.start = EXYNOS4_PA_SYSMMU_MFC_L,
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.end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[29] = {
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.start = IRQ_SYSMMU_MFC_M0_0,
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.end = IRQ_SYSMMU_MFC_M0_0,
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.flags = IORESOURCE_IRQ,
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},
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[30] = {
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.start = EXYNOS4_PA_SYSMMU_MFC_R,
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.end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[31] = {
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.start = IRQ_SYSMMU_MFC_M1_0,
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.end = IRQ_SYSMMU_MFC_M1_0,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device exynos4_device_sysmmu = {
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.name = "s5p-sysmmu",
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.id = 32,
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.num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
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.resource = exynos4_sysmmu_resource,
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};
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EXPORT_SYMBOL(exynos4_device_sysmmu);
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static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
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void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
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{
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sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
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if (IS_ERR(sysmmu_clk[ips]))
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sysmmu_clk[ips] = NULL;
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else
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clk_put(sysmmu_clk[ips]);
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}
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void sysmmu_clk_enable(sysmmu_ips ips)
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{
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if (sysmmu_clk[ips])
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clk_enable(sysmmu_clk[ips]);
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}
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void sysmmu_clk_disable(sysmmu_ips ips)
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{
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if (sysmmu_clk[ips])
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clk_disable(sysmmu_clk[ips]);
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}
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