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e34645f458
Add SMP support for i.MX7D, including CPU hotplug support, for systems where TFA is not present. The motivation for bringing up the second i.MX7D core inside the kernel is that legacy vendor bootloaders usually do not implement PSCI support. This is a significant blocker for systems in the field that are running old bootloader versions to upgrade to a modern mainline kernel version, as only one CPU of the i.MX7D would be brought up. Bring up the second i.MX7D core inside the kernel to make the migration path to mainline kernel easier for the existing iMX7D users. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com> # Fix merge conflicts Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> # heavy cleanup Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
36 lines
731 B
ArmAsm
36 lines
731 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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diag_reg_offset:
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.word g_diag_reg - .
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.macro set_diag_reg
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adr r0, diag_reg_offset
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ldr r1, [r0]
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add r1, r1, r0 @ r1 = physical &g_diag_reg
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ldr r0, [r1]
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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.endm
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ENTRY(v7_secondary_startup)
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ARM_BE8(setend be) @ go BE8 if entered LE
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mrc p15, 0, r0, c0, c0, 0
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lsl r0, r0, #16
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lsr r0, r0, #20
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/* 0xc07 is cortex A7's ID */
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mov r1, #0xc00
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orr r1, #0x7
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cmp r0, r1
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beq secondary_startup
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set_diag_reg
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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