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4350147a81
CPU freq support using 970FX powertune facility for iMac G5 and SMU based single CPU desktop. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
324 lines
8.5 KiB
C
324 lines
8.5 KiB
C
/*
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* Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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* and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
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* that is iMac G5 and latest single CPU desktop.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <linux/init.h>
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#include <linux/completion.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/sections.h>
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#include <asm/cputable.h>
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#include <asm/time.h>
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#include <asm/smu.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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/* see 970FX user manual */
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#define SCOM_PCR 0x0aa001 /* PCR scom addr */
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#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
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#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
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#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
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#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
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#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
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#define PCR_SPEED_SHIFT 17
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#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
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#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
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#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
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#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
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#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
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#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
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#define SCOM_PSR 0x408001 /* PSR scom addr */
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/* warning: PSR is a 64 bits register */
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#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
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#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
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#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
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#define PSR_CUR_SPEED_SHIFT (56)
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/*
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* The G5 only supports two frequencies (Quarter speed is not supported)
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*/
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#define CPUFREQ_HIGH 0
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#define CPUFREQ_LOW 1
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static struct cpufreq_frequency_table g5_cpu_freqs[] = {
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{CPUFREQ_HIGH, 0},
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{CPUFREQ_LOW, 0},
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{0, CPUFREQ_TABLE_END},
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};
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static struct freq_attr* g5_cpu_freqs_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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/* Power mode data is an array of the 32 bits PCR values to use for
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* the various frequencies, retreived from the device-tree
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*/
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static u32 *g5_pmode_data;
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static int g5_pmode_max;
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static int g5_pmode_cur;
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static DECLARE_MUTEX(g5_switch_mutex);
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static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
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static int g5_fvt_count; /* number of op. points */
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static int g5_fvt_cur; /* current op. point */
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/* ----------------- real hardware interface */
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static void g5_switch_volt(int speed_mode)
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{
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struct smu_simple_cmd cmd;
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DECLARE_COMPLETION(comp);
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smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
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&comp, 'V', 'S', 'L', 'E', 'W',
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0xff, g5_fvt_cur+1, speed_mode);
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wait_for_completion(&comp);
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}
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static int g5_switch_freq(int speed_mode)
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{
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struct cpufreq_freqs freqs;
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int to;
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if (g5_pmode_cur == speed_mode)
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return 0;
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down(&g5_switch_mutex);
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freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
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freqs.new = g5_cpu_freqs[speed_mode].frequency;
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freqs.cpu = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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/* If frequency is going up, first ramp up the voltage */
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if (speed_mode < g5_pmode_cur)
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g5_switch_volt(speed_mode);
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/* Clear PCR high */
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scom970_write(SCOM_PCR, 0);
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/* Clear PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
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/* Set PCR low */
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scom970_write(SCOM_PCR, PCR_HILO_SELECT |
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g5_pmode_data[speed_mode]);
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/* Wait for completion */
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for (to = 0; to < 10; to++) {
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unsigned long psr = scom970_read(SCOM_PSR);
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if ((psr & PSR_CMD_RECEIVED) == 0 &&
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(((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
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== 0)
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break;
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if (psr & PSR_CMD_COMPLETED)
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break;
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udelay(100);
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}
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/* If frequency is going down, last ramp the voltage */
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if (speed_mode > g5_pmode_cur)
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g5_switch_volt(speed_mode);
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g5_pmode_cur = speed_mode;
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ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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up(&g5_switch_mutex);
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return 0;
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}
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static int g5_query_freq(void)
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{
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unsigned long psr = scom970_read(SCOM_PSR);
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int i;
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for (i = 0; i <= g5_pmode_max; i++)
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if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
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(g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
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break;
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return i;
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}
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/* ----------------- cpufreq bookkeeping */
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static int g5_cpufreq_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
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}
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static int g5_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int newstate = 0;
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if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
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target_freq, relation, &newstate))
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return -EINVAL;
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return g5_switch_freq(newstate);
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}
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static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
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{
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return g5_cpu_freqs[g5_pmode_cur].frequency;
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}
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static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -ENODEV;
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
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policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
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cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy,
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g5_cpu_freqs);
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}
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static struct cpufreq_driver g5_cpufreq_driver = {
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.name = "powermac",
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.owner = THIS_MODULE,
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.flags = CPUFREQ_CONST_LOOPS,
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.init = g5_cpufreq_cpu_init,
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.verify = g5_cpufreq_verify,
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.target = g5_cpufreq_target,
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.get = g5_cpufreq_get_speed,
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.attr = g5_cpu_freqs_attr,
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};
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static int __init g5_cpufreq_init(void)
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{
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struct device_node *cpunode;
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unsigned int psize, ssize;
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struct smu_sdbp_header *shdr;
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unsigned long max_freq;
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u32 *valp;
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int rc = -ENODEV;
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/* Look for CPU and SMU nodes */
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cpunode = of_find_node_by_type(NULL, "cpu");
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if (!cpunode) {
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DBG("No CPU node !\n");
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return -ENODEV;
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}
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/* Check 970FX for now */
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valp = (u32 *)get_property(cpunode, "cpu-version", NULL);
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if (!valp) {
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DBG("No cpu-version property !\n");
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goto bail_noprops;
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}
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if (((*valp) >> 16) != 0x3c) {
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DBG("Wrong CPU version: %08x\n", *valp);
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goto bail_noprops;
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}
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/* Look for the powertune data in the device-tree */
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g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize);
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if (!g5_pmode_data) {
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DBG("No power-mode-data !\n");
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goto bail_noprops;
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}
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g5_pmode_max = psize / sizeof(u32) - 1;
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/* Look for the FVT table */
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shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
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if (!shdr)
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goto bail_noprops;
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g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
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ssize = (shdr->len * sizeof(u32)) - sizeof(struct smu_sdbp_header);
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g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
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g5_fvt_cur = 0;
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/* Sanity checking */
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if (g5_fvt_count < 1 || g5_pmode_max < 1)
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goto bail_noprops;
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/*
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* From what I see, clock-frequency is always the maximal frequency.
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* The current driver can not slew sysclk yet, so we really only deal
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* with powertune steps for now. We also only implement full freq and
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* half freq in this version. So far, I haven't yet seen a machine
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* supporting anything else.
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*/
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valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
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if (!valp)
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return -ENODEV;
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max_freq = (*valp)/1000;
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g5_cpu_freqs[0].frequency = max_freq;
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g5_cpu_freqs[1].frequency = max_freq/2;
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/* Check current frequency */
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g5_pmode_cur = g5_query_freq();
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if (g5_pmode_cur > 1)
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/* We don't support anything but 1:1 and 1:2, fixup ... */
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g5_pmode_cur = 1;
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/* Force apply current frequency to make sure everything is in
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* sync (voltage is right for example). Firmware may leave us with
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* a strange setting ...
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*/
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g5_switch_freq(g5_pmode_cur);
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printk(KERN_INFO "Registering G5 CPU frequency driver\n");
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printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
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g5_cpu_freqs[1].frequency/1000,
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g5_cpu_freqs[0].frequency/1000,
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g5_cpu_freqs[g5_pmode_cur].frequency/1000);
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rc = cpufreq_register_driver(&g5_cpufreq_driver);
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/* We keep the CPU node on hold... hopefully, Apple G5 don't have
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* hotplug CPU with a dynamic device-tree ...
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*/
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return rc;
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bail_noprops:
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of_node_put(cpunode);
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return rc;
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}
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module_init(g5_cpufreq_init);
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MODULE_LICENSE("GPL");
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