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0113ab803a
The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
224 lines
6.1 KiB
C
224 lines
6.1 KiB
C
/*
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* Allwinner A1X SoCs timer handling.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "timer-of.h"
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) BIT(val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE BIT(0)
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#define TIMER_CTL_RELOAD BIT(1)
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#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
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#define TIMER_CTL_CLK_SRC_OSC24M (1)
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#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
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#define TIMER_CTL_ONESHOT BIT(7)
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#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
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#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
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#define TIMER_SYNC_TICKS 3
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/*
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* When we disable a timer, we need to wait at least for 2 cycles of
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* the timer source clock. We will use for that the clocksource timer
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* that is already setup and runs at the same frequency than the other
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* timers, and we never will be disabled.
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*/
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static void sun4i_clkevt_sync(void __iomem *base)
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{
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u32 old = readl(base + TIMER_CNTVAL_REG(1));
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while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
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cpu_relax();
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}
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static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
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{
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u32 val = readl(base + TIMER_CTL_REG(timer));
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writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
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sun4i_clkevt_sync(base);
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}
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static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
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unsigned long delay)
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{
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writel(delay, base + TIMER_INTVAL_REG(timer));
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}
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static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
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bool periodic)
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{
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u32 val = readl(base + TIMER_CTL_REG(timer));
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if (periodic)
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val &= ~TIMER_CTL_ONESHOT;
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else
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val |= TIMER_CTL_ONESHOT;
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writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
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base + TIMER_CTL_REG(timer));
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}
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static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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return 0;
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}
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static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_start(timer_of_base(to), 0, false);
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return 0;
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}
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static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
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sun4i_clkevt_time_start(timer_of_base(to), 0, true);
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return 0;
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}
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static int sun4i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *clkevt)
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{
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struct timer_of *to = to_timer_of(clkevt);
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sun4i_clkevt_time_stop(timer_of_base(to), 0);
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sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
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sun4i_clkevt_time_start(timer_of_base(to), 0, false);
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return 0;
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}
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static void sun4i_timer_clear_interrupt(void __iomem *base)
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{
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writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
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}
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static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(evt);
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sun4i_timer_clear_interrupt(timer_of_base(to));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
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.clkevt = {
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.name = "sun4i_tick",
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.rating = 350,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = sun4i_clkevt_shutdown,
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.set_state_periodic = sun4i_clkevt_set_periodic,
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.set_state_oneshot = sun4i_clkevt_set_oneshot,
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.tick_resume = sun4i_clkevt_shutdown,
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.set_next_event = sun4i_clkevt_next_event,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.handler = sun4i_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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};
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static u64 notrace sun4i_timer_sched_read(void)
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{
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return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
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}
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static int __init sun4i_timer_init(struct device_node *node)
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{
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int ret;
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u32 val;
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ret = timer_of_init(node, &to);
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if (ret)
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return ret;
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writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
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writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
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TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_of_base(&to) + TIMER_CTL_REG(1));
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/*
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* sched_clock_register does not have priorities, and on sun6i and
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* later there is a better sched_clock registered by arm_arch_timer.c
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*/
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if (of_machine_is_compatible("allwinner,sun4i-a10") ||
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of_machine_is_compatible("allwinner,sun5i-a13") ||
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of_machine_is_compatible("allwinner,sun5i-a10s") ||
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of_machine_is_compatible("allwinner,suniv-f1c100s"))
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sched_clock_register(sun4i_timer_sched_read, 32,
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timer_of_rate(&to));
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ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
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node->name, timer_of_rate(&to), 350, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
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timer_of_base(&to) + TIMER_CTL_REG(0));
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/* Make sure timer is stopped before playing with interrupts */
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sun4i_clkevt_time_stop(timer_of_base(&to), 0);
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/* clear timer0 interrupt */
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sun4i_timer_clear_interrupt(timer_of_base(&to));
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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/* Enable timer0 interrupt */
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val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
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return ret;
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}
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TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
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sun4i_timer_init);
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TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
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sun4i_timer_init);
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