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5dac33ad6f
The DMA API generally relies on a struct device to work properly, and only barely works without one for legacy reasons. Pass the easily available struct device from the platform_device to remedy this. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: David S. Miller <davem@davemloft.net>
332 lines
10 KiB
C
332 lines
10 KiB
C
/* MOXA ART Ethernet (RTL8201CP) driver.
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*
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* Copyright (C) 2013 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* Based on code from
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* Moxa Technology Co., Ltd. <www.moxa.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef _MOXART_ETHERNET_H
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#define _MOXART_ETHERNET_H
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#define TX_REG_OFFSET_DESC0 0
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#define TX_REG_OFFSET_DESC1 4
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#define TX_REG_OFFSET_DESC2 8
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#define TX_REG_DESC_SIZE 16
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#define RX_REG_OFFSET_DESC0 0
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#define RX_REG_OFFSET_DESC1 4
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#define RX_REG_OFFSET_DESC2 8
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#define RX_REG_DESC_SIZE 16
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#define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
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#define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
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#define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
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#define TX_DESC1_BUF_SIZE_MASK 0x7ff
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#define TX_DESC1_LTS 0x8000000 /* last TX packet */
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#define TX_DESC1_FTS 0x10000000 /* first TX packet */
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#define TX_DESC1_FIFO_COMPLETE 0x20000000
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#define TX_DESC1_INTR_COMPLETE 0x40000000
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#define TX_DESC1_END 0x80000000
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#define TX_DESC2_ADDRESS_PHYS 0
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#define TX_DESC2_ADDRESS_VIRT 4
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#define RX_DESC0_FRAME_LEN 0
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#define RX_DESC0_FRAME_LEN_MASK 0x7FF
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#define RX_DESC0_MULTICAST 0x10000
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#define RX_DESC0_BROADCAST 0x20000
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#define RX_DESC0_ERR 0x40000
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#define RX_DESC0_CRC_ERR 0x80000
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#define RX_DESC0_FTL 0x100000
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#define RX_DESC0_RUNT 0x200000 /* packet less than 64 bytes */
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#define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */
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#define RX_DESC0_LRS 0x10000000 /* last receive segment */
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#define RX_DESC0_FRS 0x20000000 /* first receive segment */
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#define RX_DESC0_DMA_OWN 0x80000000
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#define RX_DESC1_BUF_SIZE_MASK 0x7FF
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#define RX_DESC1_END 0x80000000
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#define RX_DESC2_ADDRESS_PHYS 0
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#define RX_DESC2_ADDRESS_VIRT 4
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#define TX_DESC_NUM 64
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#define TX_DESC_NUM_MASK (TX_DESC_NUM - 1)
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#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM_MASK))
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#define TX_BUF_SIZE 1600
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#define TX_BUF_SIZE_MAX (TX_DESC1_BUF_SIZE_MASK + 1)
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#define TX_WAKE_THRESHOLD 16
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#define RX_DESC_NUM 64
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#define RX_DESC_NUM_MASK (RX_DESC_NUM - 1)
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#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM_MASK))
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#define RX_BUF_SIZE 1600
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#define RX_BUF_SIZE_MAX (RX_DESC1_BUF_SIZE_MASK + 1)
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#define REG_INTERRUPT_STATUS 0
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#define REG_INTERRUPT_MASK 4
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#define REG_MAC_MS_ADDRESS 8
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#define REG_MAC_LS_ADDRESS 12
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#define REG_MCAST_HASH_TABLE0 16
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#define REG_MCAST_HASH_TABLE1 20
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#define REG_TX_POLL_DEMAND 24
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#define REG_RX_POLL_DEMAND 28
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#define REG_TXR_BASE_ADDRESS 32
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#define REG_RXR_BASE_ADDRESS 36
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#define REG_INT_TIMER_CTRL 40
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#define REG_APOLL_TIMER_CTRL 44
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#define REG_DMA_BLEN_CTRL 48
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#define REG_RESERVED1 52
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#define REG_MAC_CTRL 136
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#define REG_MAC_STATUS 140
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#define REG_PHY_CTRL 144
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#define REG_PHY_WRITE_DATA 148
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#define REG_FLOW_CTRL 152
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#define REG_BACK_PRESSURE 156
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#define REG_RESERVED2 160
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#define REG_TEST_SEED 196
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#define REG_DMA_FIFO_STATE 200
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#define REG_TEST_MODE 204
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#define REG_RESERVED3 208
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#define REG_TX_COL_COUNTER 212
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#define REG_RPF_AEP_COUNTER 216
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#define REG_XM_PG_COUNTER 220
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#define REG_RUNT_TLC_COUNTER 224
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#define REG_CRC_FTL_COUNTER 228
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#define REG_RLC_RCC_COUNTER 232
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#define REG_BROC_COUNTER 236
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#define REG_MULCA_COUNTER 240
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#define REG_RP_COUNTER 244
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#define REG_XP_COUNTER 248
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#define REG_PHY_CTRL_OFFSET 0x0
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#define REG_PHY_STATUS 0x1
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#define REG_PHY_ID1 0x2
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#define REG_PHY_ID2 0x3
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#define REG_PHY_ANA 0x4
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#define REG_PHY_ANLPAR 0x5
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#define REG_PHY_ANE 0x6
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#define REG_PHY_ECTRL1 0x10
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#define REG_PHY_QPDS 0x11
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#define REG_PHY_10BOP 0x12
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#define REG_PHY_ECTRL2 0x13
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#define REG_PHY_FTMAC100_WRITE 0x8000000
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#define REG_PHY_FTMAC100_READ 0x4000000
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/* REG_INTERRUPT_STATUS */
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#define RPKT_FINISH BIT(0) /* DMA data received */
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#define NORXBUF BIT(1) /* receive buffer unavailable */
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#define XPKT_FINISH BIT(2) /* DMA moved data to TX FIFO */
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#define NOTXBUF BIT(3) /* transmit buffer unavailable */
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#define XPKT_OK_INT_STS BIT(4) /* transmit to ethernet success */
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#define XPKT_LOST_INT_STS BIT(5) /* transmit ethernet lost (collision) */
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#define RPKT_SAV BIT(6) /* FIFO receive success */
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#define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
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#define AHB_ERR BIT(8) /* AHB error */
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#define PHYSTS_CHG BIT(9) /* PHY link status change */
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/* REG_INTERRUPT_MASK */
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#define RPKT_FINISH_M BIT(0)
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#define NORXBUF_M BIT(1)
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#define XPKT_FINISH_M BIT(2)
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#define NOTXBUF_M BIT(3)
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#define XPKT_OK_M BIT(4)
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#define XPKT_LOST_M BIT(5)
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#define RPKT_SAV_M BIT(6)
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#define RPKT_LOST_M BIT(7)
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#define AHB_ERR_M BIT(8)
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#define PHYSTS_CHG_M BIT(9)
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/* REG_MAC_MS_ADDRESS */
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#define MAC_MADR_MASK 0xffff /* 2 MSB MAC address */
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/* REG_INT_TIMER_CTRL */
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#define TXINT_TIME_SEL BIT(15) /* TX cycle time period */
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#define TXINT_THR_MASK 0x7000
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#define TXINT_CNT_MASK 0xf00
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#define RXINT_TIME_SEL BIT(7) /* RX cycle time period */
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#define RXINT_THR_MASK 0x70
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#define RXINT_CNT_MASK 0xF
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/* REG_APOLL_TIMER_CTRL */
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#define TXPOLL_TIME_SEL BIT(12) /* TX poll time period */
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#define TXPOLL_CNT_MASK 0xf00
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#define TXPOLL_CNT_SHIFT_BIT 8
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#define RXPOLL_TIME_SEL BIT(4) /* RX poll time period */
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#define RXPOLL_CNT_MASK 0xF
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#define RXPOLL_CNT_SHIFT_BIT 0
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/* REG_DMA_BLEN_CTRL */
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#define RX_THR_EN BIT(9) /* RX FIFO threshold arbitration */
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#define RXFIFO_HTHR_MASK 0x1c0
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#define RXFIFO_LTHR_MASK 0x38
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#define INCR16_EN BIT(2) /* AHB bus INCR16 burst command */
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#define INCR8_EN BIT(1) /* AHB bus INCR8 burst command */
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#define INCR4_EN BIT(0) /* AHB bus INCR4 burst command */
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/* REG_MAC_CTRL */
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#define RX_BROADPKT BIT(17) /* receive broadcast packets */
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#define RX_MULTIPKT BIT(16) /* receive all multicast packets */
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#define FULLDUP BIT(15) /* full duplex */
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#define CRC_APD BIT(14) /* append CRC to transmitted packet */
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#define RCV_ALL BIT(12) /* ignore incoming packet destination */
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#define RX_FTL BIT(11) /* accept packets larger than 1518 B */
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#define RX_RUNT BIT(10) /* accept packets smaller than 64 B */
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#define HT_MULTI_EN BIT(9) /* accept on hash and mcast pass */
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#define RCV_EN BIT(8) /* receiver enable */
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#define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */
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#define XMT_EN BIT(5) /* transmit enable */
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#define CRC_DIS BIT(4) /* disable CRC check when receiving */
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#define LOOP_EN BIT(3) /* internal loop-back */
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#define SW_RST BIT(2) /* software reset, last 64 AHB clocks */
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#define RDMA_EN BIT(1) /* enable receive DMA chan */
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#define XDMA_EN BIT(0) /* enable transmit DMA chan */
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/* REG_MAC_STATUS */
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#define COL_EXCEED BIT(11) /* more than 16 collisions */
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#define LATE_COL BIT(10) /* transmit late collision detected */
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#define XPKT_LOST BIT(9) /* transmit to ethernet lost */
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#define XPKT_OK BIT(8) /* transmit to ethernet success */
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#define RUNT_MAC_STS BIT(7) /* receive runt detected */
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#define FTL_MAC_STS BIT(6) /* receive frame too long detected */
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#define CRC_ERR_MAC_STS BIT(5)
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#define RPKT_LOST BIT(4) /* RX FIFO full, receive failed */
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#define RPKT_SAVE BIT(3) /* RX FIFO receive success */
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#define COL BIT(2) /* collision, incoming packet dropped */
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#define MCPU_BROADCAST BIT(1)
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#define MCPU_MULTICAST BIT(0)
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/* REG_PHY_CTRL */
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#define MIIWR BIT(27) /* init write sequence (auto cleared)*/
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#define MIIRD BIT(26)
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#define REGAD_MASK 0x3e00000
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#define PHYAD_MASK 0x1f0000
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#define MIIRDATA_MASK 0xffff
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/* REG_PHY_WRITE_DATA */
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#define MIIWDATA_MASK 0xffff
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/* REG_FLOW_CTRL */
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#define PAUSE_TIME_MASK 0xffff0000
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#define FC_HIGH_MASK 0xf000
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#define FC_LOW_MASK 0xf00
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#define RX_PAUSE BIT(4) /* receive pause frame */
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#define TX_PAUSED BIT(3) /* transmit pause due to receive */
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#define FCTHR_EN BIT(2) /* enable threshold mode. */
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#define TX_PAUSE BIT(1) /* transmit pause frame */
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#define FC_EN BIT(0) /* flow control mode enable */
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/* REG_BACK_PRESSURE */
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#define BACKP_LOW_MASK 0xf00
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#define BACKP_JAM_LEN_MASK 0xf0
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#define BACKP_MODE BIT(1) /* address mode */
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#define BACKP_ENABLE BIT(0)
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/* REG_TEST_SEED */
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#define TEST_SEED_MASK 0x3fff
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/* REG_DMA_FIFO_STATE */
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#define TX_DMA_REQUEST BIT(31)
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#define RX_DMA_REQUEST BIT(30)
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#define TX_DMA_GRANT BIT(29)
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#define RX_DMA_GRANT BIT(28)
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#define TX_FIFO_EMPTY BIT(27)
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#define RX_FIFO_EMPTY BIT(26)
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#define TX_DMA2_SM_MASK 0x7000
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#define TX_DMA1_SM_MASK 0xf00
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#define RX_DMA2_SM_MASK 0x70
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#define RX_DMA1_SM_MASK 0xF
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/* REG_TEST_MODE */
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#define SINGLE_PKT BIT(26) /* single packet mode */
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#define PTIMER_TEST BIT(25) /* automatic polling timer test mode */
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#define ITIMER_TEST BIT(24) /* interrupt timer test mode */
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#define TEST_SEED_SELECT BIT(22)
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#define SEED_SELECT BIT(21)
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#define TEST_MODE BIT(20)
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#define TEST_TIME_MASK 0xffc00
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#define TEST_EXCEL_MASK 0x3e0
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/* REG_TX_COL_COUNTER */
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#define TX_MCOL_MASK 0xffff0000
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#define TX_MCOL_SHIFT_BIT 16
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#define TX_SCOL_MASK 0xffff
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#define TX_SCOL_SHIFT_BIT 0
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/* REG_RPF_AEP_COUNTER */
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#define RPF_MASK 0xffff0000
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#define RPF_SHIFT_BIT 16
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#define AEP_MASK 0xffff
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#define AEP_SHIFT_BIT 0
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/* REG_XM_PG_COUNTER */
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#define XM_MASK 0xffff0000
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#define XM_SHIFT_BIT 16
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#define PG_MASK 0xffff
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#define PG_SHIFT_BIT 0
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/* REG_RUNT_TLC_COUNTER */
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#define RUNT_CNT_MASK 0xffff0000
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#define RUNT_CNT_SHIFT_BIT 16
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#define TLCC_MASK 0xffff
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#define TLCC_SHIFT_BIT 0
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/* REG_CRC_FTL_COUNTER */
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#define CRCER_CNT_MASK 0xffff0000
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#define CRCER_CNT_SHIFT_BIT 16
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#define FTL_CNT_MASK 0xffff
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#define FTL_CNT_SHIFT_BIT 0
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/* REG_RLC_RCC_COUNTER */
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#define RLC_MASK 0xffff0000
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#define RLC_SHIFT_BIT 16
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#define RCC_MASK 0xffff
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#define RCC_SHIFT_BIT 0
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/* REG_PHY_STATUS */
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#define AN_COMPLETE 0x20
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#define LINK_STATUS 0x4
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struct moxart_mac_priv_t {
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struct platform_device *pdev;
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void __iomem *base;
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unsigned int reg_maccr;
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unsigned int reg_imr;
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struct napi_struct napi;
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struct net_device *ndev;
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dma_addr_t rx_base;
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dma_addr_t rx_mapping[RX_DESC_NUM];
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void *rx_desc_base;
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unsigned char *rx_buf_base;
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unsigned char *rx_buf[RX_DESC_NUM];
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unsigned int rx_head;
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unsigned int rx_buf_size;
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dma_addr_t tx_base;
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dma_addr_t tx_mapping[TX_DESC_NUM];
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void *tx_desc_base;
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unsigned char *tx_buf_base;
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unsigned char *tx_buf[RX_DESC_NUM];
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unsigned int tx_head;
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unsigned int tx_buf_size;
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spinlock_t txlock;
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unsigned int tx_len[TX_DESC_NUM];
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struct sk_buff *tx_skb[TX_DESC_NUM];
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unsigned int tx_tail;
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};
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#if TX_BUF_SIZE >= TX_BUF_SIZE_MAX
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#error MOXA ART Ethernet device driver TX buffer is too large!
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#endif
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#if RX_BUF_SIZE >= RX_BUF_SIZE_MAX
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#error MOXA ART Ethernet device driver RX buffer is too large!
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#endif
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#endif
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