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d27de0ef5e
We can increase the efficiency of rx path by using buffers to receive packets then build SKBs around them just before passing into the network stack. In contrast, preallocating SKBs too early reduces CPU cache efficiency. Check if we're in NAPI context when refilling RX. Normally we're almost always running in NAPI context. Dispatch to napi_alloc_frag directly instead of relying on netdev_alloc_frag which does the same but with the overhead of local_bh_disable/enable. Tested on BCM6328 320 MHz and iperf3 -M 512 to measure packet/sec performance. Included netif_receive_skb_list and NET_IP_ALIGN optimizations. Before: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-10.00 sec 49.9 MBytes 41.9 Mbits/sec 197 sender [ 4] 0.00-10.00 sec 49.3 MBytes 41.3 Mbits/sec receiver After: [ ID] Interval Transfer Bandwidth Retr [ 4] 0.00-30.00 sec 171 MBytes 47.8 Mbits/sec 272 sender [ 4] 0.00-30.00 sec 170 MBytes 47.6 Mbits/sec receiver Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
363 lines
8.1 KiB
C
363 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef BCM63XX_ENET_H_
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#define BCM63XX_ENET_H_
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#include <linux/types.h>
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#include <linux/mii.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_iudma.h>
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/* default number of descriptor */
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#define BCMENET_DEF_RX_DESC 64
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#define BCMENET_DEF_TX_DESC 32
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/* maximum burst len for dma (4 bytes unit) */
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#define BCMENET_DMA_MAXBURST 16
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#define BCMENETSW_DMA_MAXBURST 8
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/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
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* must be low enough so that a DMA transfer of above burst length can
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* not overflow the fifo */
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#define BCMENET_TX_FIFO_TRESH 32
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/*
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* hardware maximum rx/tx packet size including FCS, max mtu is
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* actually 2047, but if we set max rx size register to 2047 we won't
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* get overflow information if packet size is 2048 or above
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*/
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#define BCMENET_MAX_MTU 2046
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/*
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* MIB Counters register definitions
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*/
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#define ETH_MIB_TX_GD_OCTETS 0
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#define ETH_MIB_TX_GD_PKTS 1
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#define ETH_MIB_TX_ALL_OCTETS 2
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#define ETH_MIB_TX_ALL_PKTS 3
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#define ETH_MIB_TX_BRDCAST 4
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#define ETH_MIB_TX_MULT 5
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#define ETH_MIB_TX_64 6
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#define ETH_MIB_TX_65_127 7
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#define ETH_MIB_TX_128_255 8
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#define ETH_MIB_TX_256_511 9
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#define ETH_MIB_TX_512_1023 10
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#define ETH_MIB_TX_1024_MAX 11
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#define ETH_MIB_TX_JAB 12
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#define ETH_MIB_TX_OVR 13
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#define ETH_MIB_TX_FRAG 14
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#define ETH_MIB_TX_UNDERRUN 15
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#define ETH_MIB_TX_COL 16
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#define ETH_MIB_TX_1_COL 17
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#define ETH_MIB_TX_M_COL 18
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#define ETH_MIB_TX_EX_COL 19
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#define ETH_MIB_TX_LATE 20
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#define ETH_MIB_TX_DEF 21
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#define ETH_MIB_TX_CRS 22
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#define ETH_MIB_TX_PAUSE 23
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#define ETH_MIB_RX_GD_OCTETS 32
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#define ETH_MIB_RX_GD_PKTS 33
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#define ETH_MIB_RX_ALL_OCTETS 34
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#define ETH_MIB_RX_ALL_PKTS 35
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#define ETH_MIB_RX_BRDCAST 36
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#define ETH_MIB_RX_MULT 37
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#define ETH_MIB_RX_64 38
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#define ETH_MIB_RX_65_127 39
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#define ETH_MIB_RX_128_255 40
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#define ETH_MIB_RX_256_511 41
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#define ETH_MIB_RX_512_1023 42
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#define ETH_MIB_RX_1024_MAX 43
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#define ETH_MIB_RX_JAB 44
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#define ETH_MIB_RX_OVR 45
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#define ETH_MIB_RX_FRAG 46
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#define ETH_MIB_RX_DROP 47
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#define ETH_MIB_RX_CRC_ALIGN 48
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#define ETH_MIB_RX_UND 49
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#define ETH_MIB_RX_CRC 50
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#define ETH_MIB_RX_ALIGN 51
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#define ETH_MIB_RX_SYM 52
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#define ETH_MIB_RX_PAUSE 53
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#define ETH_MIB_RX_CNTRL 54
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/*
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* SW MIB Counters register definitions
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*/
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#define ETHSW_MIB_TX_ALL_OCT 0
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#define ETHSW_MIB_TX_DROP_PKTS 2
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#define ETHSW_MIB_TX_QOS_PKTS 3
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#define ETHSW_MIB_TX_BRDCAST 4
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#define ETHSW_MIB_TX_MULT 5
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#define ETHSW_MIB_TX_UNI 6
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#define ETHSW_MIB_TX_COL 7
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#define ETHSW_MIB_TX_1_COL 8
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#define ETHSW_MIB_TX_M_COL 9
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#define ETHSW_MIB_TX_DEF 10
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#define ETHSW_MIB_TX_LATE 11
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#define ETHSW_MIB_TX_EX_COL 12
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#define ETHSW_MIB_TX_PAUSE 14
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#define ETHSW_MIB_TX_QOS_OCT 15
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#define ETHSW_MIB_RX_ALL_OCT 17
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#define ETHSW_MIB_RX_UND 19
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#define ETHSW_MIB_RX_PAUSE 20
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#define ETHSW_MIB_RX_64 21
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#define ETHSW_MIB_RX_65_127 22
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#define ETHSW_MIB_RX_128_255 23
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#define ETHSW_MIB_RX_256_511 24
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#define ETHSW_MIB_RX_512_1023 25
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#define ETHSW_MIB_RX_1024_1522 26
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#define ETHSW_MIB_RX_OVR 27
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#define ETHSW_MIB_RX_JAB 28
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#define ETHSW_MIB_RX_ALIGN 29
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#define ETHSW_MIB_RX_CRC 30
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#define ETHSW_MIB_RX_GD_OCT 31
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#define ETHSW_MIB_RX_DROP 33
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#define ETHSW_MIB_RX_UNI 34
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#define ETHSW_MIB_RX_MULT 35
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#define ETHSW_MIB_RX_BRDCAST 36
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#define ETHSW_MIB_RX_SA_CHANGE 37
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#define ETHSW_MIB_RX_FRAG 38
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#define ETHSW_MIB_RX_OVR_DISC 39
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#define ETHSW_MIB_RX_SYM 40
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#define ETHSW_MIB_RX_QOS_PKTS 41
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#define ETHSW_MIB_RX_QOS_OCT 42
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#define ETHSW_MIB_RX_1523_2047 44
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#define ETHSW_MIB_RX_2048_4095 45
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#define ETHSW_MIB_RX_4096_8191 46
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#define ETHSW_MIB_RX_8192_9728 47
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struct bcm_enet_mib_counters {
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u64 tx_gd_octets;
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u32 tx_gd_pkts;
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u32 tx_all_octets;
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u32 tx_all_pkts;
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u32 tx_unicast;
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u32 tx_brdcast;
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u32 tx_mult;
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u32 tx_64;
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u32 tx_65_127;
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u32 tx_128_255;
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u32 tx_256_511;
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u32 tx_512_1023;
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u32 tx_1024_max;
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u32 tx_1523_2047;
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u32 tx_2048_4095;
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u32 tx_4096_8191;
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u32 tx_8192_9728;
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u32 tx_jab;
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u32 tx_drop;
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u32 tx_ovr;
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u32 tx_frag;
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u32 tx_underrun;
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u32 tx_col;
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u32 tx_1_col;
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u32 tx_m_col;
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u32 tx_ex_col;
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u32 tx_late;
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u32 tx_def;
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u32 tx_crs;
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u32 tx_pause;
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u64 rx_gd_octets;
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u32 rx_gd_pkts;
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u32 rx_all_octets;
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u32 rx_all_pkts;
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u32 rx_brdcast;
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u32 rx_unicast;
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u32 rx_mult;
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u32 rx_64;
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u32 rx_65_127;
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u32 rx_128_255;
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u32 rx_256_511;
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u32 rx_512_1023;
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u32 rx_1024_max;
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u32 rx_jab;
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u32 rx_ovr;
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u32 rx_frag;
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u32 rx_drop;
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u32 rx_crc_align;
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u32 rx_und;
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u32 rx_crc;
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u32 rx_align;
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u32 rx_sym;
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u32 rx_pause;
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u32 rx_cntrl;
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};
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struct bcm_enet_priv {
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/* base remapped address of device */
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void __iomem *base;
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/* mac irq, rx_dma irq, tx_dma irq */
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int irq;
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int irq_rx;
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int irq_tx;
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/* hw view of rx & tx dma ring */
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dma_addr_t rx_desc_dma;
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dma_addr_t tx_desc_dma;
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/* allocated size (in bytes) for rx & tx dma ring */
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unsigned int rx_desc_alloc_size;
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unsigned int tx_desc_alloc_size;
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struct napi_struct napi;
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/* dma channel id for rx */
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int rx_chan;
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/* number of dma desc in rx ring */
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int rx_ring_size;
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/* cpu view of rx dma ring */
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struct bcm_enet_desc *rx_desc_cpu;
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/* current number of armed descriptor given to hardware for rx */
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int rx_desc_count;
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/* next rx descriptor to fetch from hardware */
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int rx_curr_desc;
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/* next dirty rx descriptor to refill */
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int rx_dirty_desc;
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/* size of allocated rx buffers */
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unsigned int rx_buf_size;
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/* allocated rx buffer offset */
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unsigned int rx_buf_offset;
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/* size of allocated rx frag */
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unsigned int rx_frag_size;
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/* list of buffer given to hw for rx */
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void **rx_buf;
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/* used when rx skb allocation failed, so we defer rx queue
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* refill */
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struct timer_list rx_timeout;
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/* lock rx_timeout against rx normal operation */
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spinlock_t rx_lock;
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/* dma channel id for tx */
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int tx_chan;
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/* number of dma desc in tx ring */
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int tx_ring_size;
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/* maximum dma burst size */
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int dma_maxburst;
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/* cpu view of rx dma ring */
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struct bcm_enet_desc *tx_desc_cpu;
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/* number of available descriptor for tx */
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int tx_desc_count;
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/* next tx descriptor avaiable */
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int tx_curr_desc;
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/* next dirty tx descriptor to reclaim */
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int tx_dirty_desc;
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/* list of skb given to hw for tx */
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struct sk_buff **tx_skb;
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/* lock used by tx reclaim and xmit */
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spinlock_t tx_lock;
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/* set if internal phy is ignored and external mii interface
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* is selected */
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int use_external_mii;
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/* set if a phy is connected, phy address must be known,
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* probing is not possible */
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int has_phy;
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int phy_id;
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/* set if connected phy has an associated irq */
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int has_phy_interrupt;
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int phy_interrupt;
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/* used when a phy is connected (phylib used) */
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struct mii_bus *mii_bus;
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int old_link;
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int old_duplex;
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int old_pause;
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/* used when no phy is connected */
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int force_speed_100;
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int force_duplex_full;
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/* pause parameters */
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int pause_auto;
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int pause_rx;
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int pause_tx;
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/* stats */
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struct bcm_enet_mib_counters mib;
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/* after mib interrupt, mib registers update is done in this
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* work queue */
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struct work_struct mib_update_task;
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/* lock mib update between userspace request and workqueue */
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struct mutex mib_update_lock;
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/* mac clock */
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struct clk *mac_clk;
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/* phy clock if internal phy is used */
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struct clk *phy_clk;
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/* network device reference */
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struct net_device *net_dev;
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/* platform device reference */
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struct platform_device *pdev;
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/* maximum hardware transmit/receive size */
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unsigned int hw_mtu;
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bool enet_is_sw;
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/* port mapping for switch devices */
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int num_ports;
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struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
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int sw_port_link[ENETSW_MAX_PORT];
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/* used to poll switch port state */
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struct timer_list swphy_poll;
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spinlock_t enetsw_mdio_lock;
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/* dma channel enable mask */
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u32 dma_chan_en_mask;
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/* dma channel interrupt mask */
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u32 dma_chan_int_mask;
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/* DMA engine has internal SRAM */
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bool dma_has_sram;
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/* dma channel width */
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unsigned int dma_chan_width;
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/* dma descriptor shift value */
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unsigned int dma_desc_shift;
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};
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#endif /* ! BCM63XX_ENET_H_ */
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