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32d8599968
Dan reports that smatch complains about a potential uninitialized
variable being used in the compat alignment fixup code.
The logic is not wrong per se, but we do end up using an uninitialized
variable if reading the instruction that triggered the alignment fault
from user space faults, even if the fault ensures that the uninitialized
value doesn't propagate any further.
Given that we just give up and return 1 if any fault occurs when reading
the instruction, let's get rid of the 'success handling' pattern that
captures the fault in a variable and aborts later, and instead, just
return 1 immediately if any of the get_user() calls result in an
exception.
Fixes: 3fc24ef32d ("arm64: compat: Implement misalignment fixups for multiword loads")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Link: https://lore.kernel.org/r/202304021214.gekJ8yRc-lkp@intel.com/
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20230404103625.2386382-1-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
384 lines
9.8 KiB
C
384 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// based on arch/arm/mm/alignment.c
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/perf_event.h>
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#include <linux/uaccess.h>
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#include <asm/exception.h>
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#include <asm/ptrace.h>
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#include <asm/traps.h>
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/*
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* 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
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*
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* Speed optimisations and better fault handling by Russell King.
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*/
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#define CODING_BITS(i) (i & 0x0e000000)
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#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
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#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
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#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
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#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
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#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
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#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
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#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
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#define RD_BITS(i) ((i >> 12) & 15) /* Rd */
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#define RM_BITS(i) (i & 15) /* Rm */
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#define REGMASK_BITS(i) (i & 0xffff)
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#define BAD_INSTR 0xdeadc0de
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/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
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#define IS_T32(hi16) \
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(((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
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union offset_union {
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unsigned long un;
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signed long sn;
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};
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#define TYPE_ERROR 0
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#define TYPE_FAULT 1
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#define TYPE_LDST 2
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#define TYPE_DONE 3
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static void
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do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs,
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union offset_union offset)
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{
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if (!LDST_U_BIT(instr))
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offset.un = -offset.un;
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if (!LDST_P_BIT(instr))
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addr += offset.un;
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if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
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regs->regs[RN_BITS(instr)] = addr;
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}
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static int
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do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs)
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{
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unsigned int rd = RD_BITS(instr);
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unsigned int rd2;
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int load;
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if ((instr & 0xfe000000) == 0xe8000000) {
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/* ARMv7 Thumb-2 32-bit LDRD/STRD */
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rd2 = (instr >> 8) & 0xf;
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load = !!(LDST_L_BIT(instr));
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} else if (((rd & 1) == 1) || (rd == 14)) {
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return TYPE_ERROR;
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} else {
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load = ((instr & 0xf0) == 0xd0);
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rd2 = rd + 1;
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}
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if (load) {
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unsigned int val, val2;
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if (get_user(val, (u32 __user *)addr) ||
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get_user(val2, (u32 __user *)(addr + 4)))
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return TYPE_FAULT;
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regs->regs[rd] = val;
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regs->regs[rd2] = val2;
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} else {
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if (put_user(regs->regs[rd], (u32 __user *)addr) ||
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put_user(regs->regs[rd2], (u32 __user *)(addr + 4)))
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return TYPE_FAULT;
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}
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return TYPE_LDST;
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}
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/*
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* LDM/STM alignment handler.
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*
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* There are 4 variants of this instruction:
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*
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* B = rn pointer before instruction, A = rn pointer after instruction
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* ------ increasing address ----->
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* | | r0 | r1 | ... | rx | |
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* PU = 01 B A
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* PU = 11 B A
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* PU = 00 A B
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* PU = 10 A B
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*/
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static int
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do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs)
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{
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unsigned int rd, rn, nr_regs, regbits;
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unsigned long eaddr, newaddr;
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unsigned int val;
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/* count the number of registers in the mask to be transferred */
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nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
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rn = RN_BITS(instr);
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newaddr = eaddr = regs->regs[rn];
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if (!LDST_U_BIT(instr))
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nr_regs = -nr_regs;
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newaddr += nr_regs;
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if (!LDST_U_BIT(instr))
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eaddr = newaddr;
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if (LDST_P_EQ_U(instr)) /* U = P */
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eaddr += 4;
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for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
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regbits >>= 1, rd += 1)
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if (regbits & 1) {
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if (LDST_L_BIT(instr)) {
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if (get_user(val, (u32 __user *)eaddr))
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return TYPE_FAULT;
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if (rd < 15)
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regs->regs[rd] = val;
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else
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regs->pc = val;
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} else {
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/*
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* The PC register has a bias of +8 in ARM mode
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* and +4 in Thumb mode. This means that a read
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* of the value of PC should account for this.
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* Since Thumb does not permit STM instructions
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* to refer to PC, just add 8 here.
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*/
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val = (rd < 15) ? regs->regs[rd] : regs->pc + 8;
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if (put_user(val, (u32 __user *)eaddr))
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return TYPE_FAULT;
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}
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eaddr += 4;
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}
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if (LDST_W_BIT(instr))
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regs->regs[rn] = newaddr;
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return TYPE_DONE;
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}
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/*
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* Convert Thumb multi-word load/store instruction forms to equivalent ARM
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* instructions so we can reuse ARM userland alignment fault fixups for Thumb.
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*
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* This implementation was initially based on the algorithm found in
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* gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
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* to convert only Thumb ld/st instruction forms to equivalent ARM forms.
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*
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* NOTES:
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* 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
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* 2. If for some reason we're passed an non-ld/st Thumb instruction to
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* decode, we return 0xdeadc0de. This should never happen under normal
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* circumstances but if it does, we've got other problems to deal with
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* elsewhere and we obviously can't fix those problems here.
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*/
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static unsigned long thumb2arm(u16 tinstr)
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{
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u32 L = (tinstr & (1<<11)) >> 11;
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switch ((tinstr & 0xf800) >> 11) {
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/* 6.6.1 Format 1: */
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case 0xc000 >> 11: /* 7.1.51 STMIA */
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case 0xc800 >> 11: /* 7.1.25 LDMIA */
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{
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u32 Rn = (tinstr & (7<<8)) >> 8;
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u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
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return 0xe8800000 | W | (L<<20) | (Rn<<16) |
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(tinstr&255);
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}
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/* 6.6.1 Format 2: */
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case 0xb000 >> 11: /* 7.1.48 PUSH */
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case 0xb800 >> 11: /* 7.1.47 POP */
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if ((tinstr & (3 << 9)) == 0x0400) {
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static const u32 subset[4] = {
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0xe92d0000, /* STMDB sp!,{registers} */
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0xe92d4000, /* STMDB sp!,{registers,lr} */
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0xe8bd0000, /* LDMIA sp!,{registers} */
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0xe8bd8000 /* LDMIA sp!,{registers,pc} */
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};
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return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
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(tinstr & 255); /* register_list */
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}
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fallthrough; /* for illegal instruction case */
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default:
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return BAD_INSTR;
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}
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}
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/*
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* Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
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* handlable by ARM alignment handler, also find the corresponding handler,
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* so that we can reuse ARM userland alignment fault fixups for Thumb.
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*
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* @pinstr: original Thumb-2 instruction; returns new handlable instruction
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* @regs: register context.
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* @poffset: return offset from faulted addr for later writeback
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*
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* NOTES:
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* 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
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* 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
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*/
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static void *
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do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
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union offset_union *poffset)
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{
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u32 instr = *pinstr;
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u16 tinst1 = (instr >> 16) & 0xffff;
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u16 tinst2 = instr & 0xffff;
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switch (tinst1 & 0xffe0) {
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/* A6.3.5 Load/Store multiple */
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case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
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case 0xe8a0: /* ...above writeback version */
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case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
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case 0xe920: /* ...above writeback version */
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/* no need offset decision since handler calculates it */
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return do_alignment_ldmstm;
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case 0xf840: /* POP/PUSH T3 (single register) */
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if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
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u32 L = !!(LDST_L_BIT(instr));
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const u32 subset[2] = {
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0xe92d0000, /* STMDB sp!,{registers} */
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0xe8bd0000, /* LDMIA sp!,{registers} */
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};
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*pinstr = subset[L] | (1<<RD_BITS(instr));
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return do_alignment_ldmstm;
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}
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/* Else fall through for illegal instruction case */
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break;
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/* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
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case 0xe860:
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case 0xe960:
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case 0xe8e0:
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case 0xe9e0:
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poffset->un = (tinst2 & 0xff) << 2;
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fallthrough;
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case 0xe940:
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case 0xe9c0:
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return do_alignment_ldrdstrd;
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/*
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* No need to handle load/store instructions up to word size
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* since ARMv6 and later CPUs can perform unaligned accesses.
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*/
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default:
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break;
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}
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return NULL;
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}
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static int alignment_get_arm(struct pt_regs *regs, __le32 __user *ip, u32 *inst)
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{
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__le32 instr = 0;
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int fault;
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fault = get_user(instr, ip);
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if (fault)
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return fault;
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*inst = __le32_to_cpu(instr);
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return 0;
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}
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static int alignment_get_thumb(struct pt_regs *regs, __le16 __user *ip, u16 *inst)
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{
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__le16 instr = 0;
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int fault;
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fault = get_user(instr, ip);
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if (fault)
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return fault;
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*inst = __le16_to_cpu(instr);
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return 0;
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}
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int do_compat_alignment_fixup(unsigned long addr, struct pt_regs *regs)
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{
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union offset_union offset;
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unsigned long instrptr;
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int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs);
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unsigned int type;
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u32 instr = 0;
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int isize = 4;
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int thumb2_32b = 0;
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instrptr = instruction_pointer(regs);
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if (compat_thumb_mode(regs)) {
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__le16 __user *ptr = (__le16 __user *)(instrptr & ~1);
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u16 tinstr, tinst2;
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if (alignment_get_thumb(regs, ptr, &tinstr))
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return 1;
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if (IS_T32(tinstr)) { /* Thumb-2 32-bit */
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if (alignment_get_thumb(regs, ptr + 1, &tinst2))
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return 1;
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instr = ((u32)tinstr << 16) | tinst2;
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thumb2_32b = 1;
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} else {
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isize = 2;
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instr = thumb2arm(tinstr);
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}
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} else {
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if (alignment_get_arm(regs, (__le32 __user *)instrptr, &instr))
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return 1;
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}
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switch (CODING_BITS(instr)) {
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case 0x00000000: /* 3.13.4 load/store instruction extensions */
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if (LDSTHD_I_BIT(instr))
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offset.un = (instr & 0xf00) >> 4 | (instr & 15);
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else
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offset.un = regs->regs[RM_BITS(instr)];
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if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
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(instr & 0x001000f0) == 0x000000f0) /* STRD */
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handler = do_alignment_ldrdstrd;
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else
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return 1;
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break;
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case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
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if (thumb2_32b) {
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offset.un = 0;
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handler = do_alignment_t32_to_handler(&instr, regs, &offset);
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} else {
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offset.un = 0;
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handler = do_alignment_ldmstm;
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}
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break;
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default:
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return 1;
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}
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type = handler(addr, instr, regs);
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if (type == TYPE_ERROR || type == TYPE_FAULT)
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return 1;
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if (type == TYPE_LDST)
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do_alignment_finish_ldst(addr, instr, regs, offset);
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->pc);
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arm64_skip_faulting_instruction(regs, isize);
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return 0;
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}
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