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842dfc11ea
Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:
{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
LD arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
arch/mips/alchemy/common/sleeper.o uses -mhard-float
To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS; but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
278 lines
7.2 KiB
ArmAsm
278 lines
7.2 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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#undef fp
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.macro EX insn, reg, src
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.set push
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SET_HARDFLOAT
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.set nomacro
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.ex\@: \insn \reg, \src
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.set pop
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.section __ex_table,"a"
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PTR .ex\@, fault
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.previous
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.endm
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.set noreorder
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.set arch=r4000
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LEAF(_save_fp_context)
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.set push
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SET_HARDFLOAT
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cfc1 t1, fcr31
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.set pop
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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.set push
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SET_HARDFLOAT
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#ifdef CONFIG_CPU_MIPS32_R2
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.set mips32r2
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.set fp=64
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip storing odd if FR=0
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nop
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#endif
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/* Store the 16 odd double precision registers */
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EX sdc1 $f1, SC_FPREGS+8(a0)
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EX sdc1 $f3, SC_FPREGS+24(a0)
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EX sdc1 $f5, SC_FPREGS+40(a0)
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EX sdc1 $f7, SC_FPREGS+56(a0)
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EX sdc1 $f9, SC_FPREGS+72(a0)
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EX sdc1 $f11, SC_FPREGS+88(a0)
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EX sdc1 $f13, SC_FPREGS+104(a0)
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EX sdc1 $f15, SC_FPREGS+120(a0)
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EX sdc1 $f17, SC_FPREGS+136(a0)
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EX sdc1 $f19, SC_FPREGS+152(a0)
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EX sdc1 $f21, SC_FPREGS+168(a0)
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EX sdc1 $f23, SC_FPREGS+184(a0)
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EX sdc1 $f25, SC_FPREGS+200(a0)
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EX sdc1 $f27, SC_FPREGS+216(a0)
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EX sdc1 $f29, SC_FPREGS+232(a0)
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EX sdc1 $f31, SC_FPREGS+248(a0)
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1: .set pop
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#endif
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.set push
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SET_HARDFLOAT
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/* Store the 16 even double precision registers */
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EX sdc1 $f0, SC_FPREGS+0(a0)
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EX sdc1 $f2, SC_FPREGS+16(a0)
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EX sdc1 $f4, SC_FPREGS+32(a0)
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EX sdc1 $f6, SC_FPREGS+48(a0)
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EX sdc1 $f8, SC_FPREGS+64(a0)
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EX sdc1 $f10, SC_FPREGS+80(a0)
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EX sdc1 $f12, SC_FPREGS+96(a0)
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EX sdc1 $f14, SC_FPREGS+112(a0)
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EX sdc1 $f16, SC_FPREGS+128(a0)
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EX sdc1 $f18, SC_FPREGS+144(a0)
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EX sdc1 $f20, SC_FPREGS+160(a0)
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EX sdc1 $f22, SC_FPREGS+176(a0)
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EX sdc1 $f24, SC_FPREGS+192(a0)
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EX sdc1 $f26, SC_FPREGS+208(a0)
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EX sdc1 $f28, SC_FPREGS+224(a0)
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EX sdc1 $f30, SC_FPREGS+240(a0)
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EX sw t1, SC_FPC_CSR(a0)
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jr ra
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li v0, 0 # success
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.set pop
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END(_save_fp_context)
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#ifdef CONFIG_MIPS32_COMPAT
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/* Save 32-bit process floating point context */
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LEAF(_save_fp_context32)
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.set push
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SET_HARDFLOAT
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cfc1 t1, fcr31
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip storing odd if FR=0
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nop
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/* Store the 16 odd double precision registers */
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EX sdc1 $f1, SC32_FPREGS+8(a0)
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EX sdc1 $f3, SC32_FPREGS+24(a0)
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EX sdc1 $f5, SC32_FPREGS+40(a0)
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EX sdc1 $f7, SC32_FPREGS+56(a0)
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EX sdc1 $f9, SC32_FPREGS+72(a0)
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EX sdc1 $f11, SC32_FPREGS+88(a0)
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EX sdc1 $f13, SC32_FPREGS+104(a0)
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EX sdc1 $f15, SC32_FPREGS+120(a0)
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EX sdc1 $f17, SC32_FPREGS+136(a0)
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EX sdc1 $f19, SC32_FPREGS+152(a0)
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EX sdc1 $f21, SC32_FPREGS+168(a0)
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EX sdc1 $f23, SC32_FPREGS+184(a0)
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EX sdc1 $f25, SC32_FPREGS+200(a0)
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EX sdc1 $f27, SC32_FPREGS+216(a0)
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EX sdc1 $f29, SC32_FPREGS+232(a0)
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EX sdc1 $f31, SC32_FPREGS+248(a0)
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/* Store the 16 even double precision registers */
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1: EX sdc1 $f0, SC32_FPREGS+0(a0)
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EX sdc1 $f2, SC32_FPREGS+16(a0)
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EX sdc1 $f4, SC32_FPREGS+32(a0)
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EX sdc1 $f6, SC32_FPREGS+48(a0)
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EX sdc1 $f8, SC32_FPREGS+64(a0)
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EX sdc1 $f10, SC32_FPREGS+80(a0)
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EX sdc1 $f12, SC32_FPREGS+96(a0)
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EX sdc1 $f14, SC32_FPREGS+112(a0)
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EX sdc1 $f16, SC32_FPREGS+128(a0)
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EX sdc1 $f18, SC32_FPREGS+144(a0)
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EX sdc1 $f20, SC32_FPREGS+160(a0)
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EX sdc1 $f22, SC32_FPREGS+176(a0)
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EX sdc1 $f24, SC32_FPREGS+192(a0)
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EX sdc1 $f26, SC32_FPREGS+208(a0)
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EX sdc1 $f28, SC32_FPREGS+224(a0)
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EX sdc1 $f30, SC32_FPREGS+240(a0)
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EX sw t1, SC32_FPC_CSR(a0)
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cfc1 t0, $0 # implementation/version
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EX sw t0, SC32_FPC_EIR(a0)
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.set pop
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jr ra
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li v0, 0 # success
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END(_save_fp_context32)
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#endif
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/*
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* Restore FPU state:
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* - fp gp registers
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* - cp1 status/control register
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*/
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LEAF(_restore_fp_context)
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EX lw t1, SC_FPC_CSR(a0)
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
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.set push
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SET_HARDFLOAT
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#ifdef CONFIG_CPU_MIPS32_R2
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.set mips32r2
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.set fp=64
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip loading odd if FR=0
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nop
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#endif
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EX ldc1 $f1, SC_FPREGS+8(a0)
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EX ldc1 $f3, SC_FPREGS+24(a0)
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EX ldc1 $f5, SC_FPREGS+40(a0)
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EX ldc1 $f7, SC_FPREGS+56(a0)
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EX ldc1 $f9, SC_FPREGS+72(a0)
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EX ldc1 $f11, SC_FPREGS+88(a0)
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EX ldc1 $f13, SC_FPREGS+104(a0)
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EX ldc1 $f15, SC_FPREGS+120(a0)
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EX ldc1 $f17, SC_FPREGS+136(a0)
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EX ldc1 $f19, SC_FPREGS+152(a0)
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EX ldc1 $f21, SC_FPREGS+168(a0)
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EX ldc1 $f23, SC_FPREGS+184(a0)
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EX ldc1 $f25, SC_FPREGS+200(a0)
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EX ldc1 $f27, SC_FPREGS+216(a0)
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EX ldc1 $f29, SC_FPREGS+232(a0)
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EX ldc1 $f31, SC_FPREGS+248(a0)
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1: .set pop
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#endif
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.set push
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SET_HARDFLOAT
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EX ldc1 $f0, SC_FPREGS+0(a0)
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EX ldc1 $f2, SC_FPREGS+16(a0)
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EX ldc1 $f4, SC_FPREGS+32(a0)
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EX ldc1 $f6, SC_FPREGS+48(a0)
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EX ldc1 $f8, SC_FPREGS+64(a0)
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EX ldc1 $f10, SC_FPREGS+80(a0)
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EX ldc1 $f12, SC_FPREGS+96(a0)
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EX ldc1 $f14, SC_FPREGS+112(a0)
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EX ldc1 $f16, SC_FPREGS+128(a0)
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EX ldc1 $f18, SC_FPREGS+144(a0)
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EX ldc1 $f20, SC_FPREGS+160(a0)
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EX ldc1 $f22, SC_FPREGS+176(a0)
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EX ldc1 $f24, SC_FPREGS+192(a0)
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EX ldc1 $f26, SC_FPREGS+208(a0)
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EX ldc1 $f28, SC_FPREGS+224(a0)
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EX ldc1 $f30, SC_FPREGS+240(a0)
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ctc1 t1, fcr31
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.set pop
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jr ra
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li v0, 0 # success
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END(_restore_fp_context)
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#ifdef CONFIG_MIPS32_COMPAT
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LEAF(_restore_fp_context32)
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/* Restore an o32 sigcontext. */
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.set push
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SET_HARDFLOAT
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EX lw t1, SC32_FPC_CSR(a0)
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip loading odd if FR=0
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nop
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EX ldc1 $f1, SC32_FPREGS+8(a0)
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EX ldc1 $f3, SC32_FPREGS+24(a0)
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EX ldc1 $f5, SC32_FPREGS+40(a0)
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EX ldc1 $f7, SC32_FPREGS+56(a0)
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EX ldc1 $f9, SC32_FPREGS+72(a0)
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EX ldc1 $f11, SC32_FPREGS+88(a0)
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EX ldc1 $f13, SC32_FPREGS+104(a0)
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EX ldc1 $f15, SC32_FPREGS+120(a0)
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EX ldc1 $f17, SC32_FPREGS+136(a0)
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EX ldc1 $f19, SC32_FPREGS+152(a0)
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EX ldc1 $f21, SC32_FPREGS+168(a0)
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EX ldc1 $f23, SC32_FPREGS+184(a0)
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EX ldc1 $f25, SC32_FPREGS+200(a0)
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EX ldc1 $f27, SC32_FPREGS+216(a0)
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EX ldc1 $f29, SC32_FPREGS+232(a0)
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EX ldc1 $f31, SC32_FPREGS+248(a0)
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1: EX ldc1 $f0, SC32_FPREGS+0(a0)
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EX ldc1 $f2, SC32_FPREGS+16(a0)
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EX ldc1 $f4, SC32_FPREGS+32(a0)
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EX ldc1 $f6, SC32_FPREGS+48(a0)
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EX ldc1 $f8, SC32_FPREGS+64(a0)
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EX ldc1 $f10, SC32_FPREGS+80(a0)
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EX ldc1 $f12, SC32_FPREGS+96(a0)
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EX ldc1 $f14, SC32_FPREGS+112(a0)
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EX ldc1 $f16, SC32_FPREGS+128(a0)
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EX ldc1 $f18, SC32_FPREGS+144(a0)
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EX ldc1 $f20, SC32_FPREGS+160(a0)
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EX ldc1 $f22, SC32_FPREGS+176(a0)
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EX ldc1 $f24, SC32_FPREGS+192(a0)
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EX ldc1 $f26, SC32_FPREGS+208(a0)
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EX ldc1 $f28, SC32_FPREGS+224(a0)
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EX ldc1 $f30, SC32_FPREGS+240(a0)
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ctc1 t1, fcr31
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jr ra
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li v0, 0 # success
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.set pop
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END(_restore_fp_context32)
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#endif
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.set reorder
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.type fault@function
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.ent fault
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fault: li v0, -EFAULT # failure
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jr ra
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.end fault
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