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e7f626db83
This patch changes the nwfpe implementation to use the new generic
ARM instruction set condition code checks, rather than a local
implementation. It also removes the existing condition code checking,
which has been used for the generic support (in kernel/opcodes.{ch}).
This code has not been tested beyond building, linking and booting.
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
125 lines
4.5 KiB
ArmAsm
125 lines
4.5 KiB
ArmAsm
/*
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NetWinder Floating Point Emulator
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(c) Rebel.COM, 1998
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(c) 1998, 1999 Philip Blundell
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Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/opcodes.h>
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/* This is the kernel's entry point into the floating point emulator.
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It is called from the kernel with code similar to this:
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sub r4, r5, #4
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ldrt r0, [r4] @ r0 = instruction
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adrsvc al, r9, ret_from_exception @ r9 = normal FP return
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adrsvc al, lr, fpundefinstr @ lr = undefined instr return
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get_current_task r10
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mov r8, #1
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strb r8, [r10, #TSK_USED_MATH] @ set current->used_math
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add r10, r10, #TSS_FPESAVE @ r10 = workspace
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ldr r4, .LC2
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ldr pc, [r4] @ Call FP emulator entry point
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The kernel expects the emulator to return via one of two possible
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points of return it passes to the emulator. The emulator, if
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successful in its emulation, jumps to ret_from_exception (passed in
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r9) and the kernel takes care of returning control from the trap to
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the user code. If the emulator is unable to emulate the instruction,
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it returns via _fpundefinstr (passed via lr) and the kernel halts the
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user program with a core dump.
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On entry to the emulator r10 points to an area of private FP workspace
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reserved in the thread structure for this process. This is where the
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emulator saves its registers across calls. The first word of this area
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is used as a flag to detect the first time a process uses floating point,
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so that the emulator startup cost can be avoided for tasks that don't
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want it.
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This routine does three things:
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1) The kernel has created a struct pt_regs on the stack and saved the
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user registers into it. See /usr/include/asm/proc/ptrace.h for details.
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2) It calls EmulateAll to emulate a floating point instruction.
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EmulateAll returns 1 if the emulation was successful, or 0 if not.
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3) If an instruction has been emulated successfully, it looks ahead at
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the next instruction. If it is a floating point instruction, it
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executes the instruction, without returning to user space. In this
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way it repeatedly looks ahead and executes floating point instructions
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until it encounters a non floating point instruction, at which time it
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returns via _fpreturn.
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This is done to reduce the effect of the trap overhead on each
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floating point instructions. GCC attempts to group floating point
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instructions to allow the emulator to spread the cost of the trap over
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several floating point instructions. */
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#include <asm/asm-offsets.h>
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.globl nwfpe_enter
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nwfpe_enter:
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mov r4, lr @ save the failure-return addresses
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mov sl, sp @ we access the registers via 'sl'
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ldr r5, [sp, #S_PC] @ get contents of PC;
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mov r6, r0 @ save the opcode
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emulate:
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ldr r1, [sp, #S_PSR] @ fetch the PSR
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bl arm_check_condition @ check the condition
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cmp r0, #ARM_OPCODE_CONDTEST_PASS @ condition passed?
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@ if condition code failed to match, next insn
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bne next @ get the next instruction;
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mov r0, r6 @ prepare for EmulateAll()
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bl EmulateAll @ emulate the instruction
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cmp r0, #0 @ was emulation successful
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moveq pc, r4 @ no, return failure
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next:
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.Lx1: ldrt r6, [r5], #4 @ get the next instruction and
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@ increment PC
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and r2, r6, #0x0F000000 @ test for FP insns
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teq r2, #0x0C000000
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teqne r2, #0x0D000000
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teqne r2, #0x0E000000
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movne pc, r9 @ return ok if not a fp insn
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str r5, [sp, #S_PC] @ update PC copy in regs
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mov r0, r6 @ save a copy
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b emulate @ check condition and emulate
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@ We need to be prepared for the instructions at .Lx1 and .Lx2
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@ to fault. Emit the appropriate exception gunk to fix things up.
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@ ??? For some reason, faults can happen at .Lx2 even with a
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@ plain LDR instruction. Weird, but it seems harmless.
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.pushsection .fixup,"ax"
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.align 2
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.Lfix: mov pc, r9 @ let the user eat segfaults
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.popsection
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.pushsection __ex_table,"a"
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.align 3
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.long .Lx1, .Lfix
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.popsection
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