mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-19 00:54:41 +08:00
ea8ca3109d
With the new clk parenting code, clk_init_data was expanded to include .parent_hws and .parent_data, for clk drivers to specify parents without name strings of clocks. Also some macros were added for using these two items to reference clock parents. Based on that to expand macros for sprd clocks: - SPRD_*_DATA, take an array of struct clk_parent_data * as its parents which should be a combination of .fw_name (devicetree clock-names), .hw (pointers to a local struct clk_hw). - SPRD_*_HW, take a local struct clk_hw pointer, instead of a string, as its parent. - SPRD_*_FW_NAME, take a string of clock-names decleared in the device tree as the clock parent. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
//
|
|
// Spreadtrum divider clock driver
|
|
//
|
|
// Copyright (C) 2017 Spreadtrum, Inc.
|
|
// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
|
|
|
|
#ifndef _SPRD_DIV_H_
|
|
#define _SPRD_DIV_H_
|
|
|
|
#include "common.h"
|
|
|
|
/**
|
|
* struct sprd_div_internal - Internal divider description
|
|
* @shift: Bit offset of the divider in its register
|
|
* @width: Width of the divider field in its register
|
|
*
|
|
* That structure represents a single divider, and is meant to be
|
|
* embedded in other structures representing the various clock
|
|
* classes.
|
|
*/
|
|
struct sprd_div_internal {
|
|
u8 shift;
|
|
u8 width;
|
|
};
|
|
|
|
#define _SPRD_DIV_CLK(_shift, _width) \
|
|
{ \
|
|
.shift = _shift, \
|
|
.width = _width, \
|
|
}
|
|
|
|
struct sprd_div {
|
|
struct sprd_div_internal div;
|
|
struct sprd_clk_common common;
|
|
};
|
|
|
|
#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
|
_shift, _width, _flags, _fn) \
|
|
struct sprd_div _struct = { \
|
|
.div = _SPRD_DIV_CLK(_shift, _width), \
|
|
.common = { \
|
|
.regmap = NULL, \
|
|
.reg = _reg, \
|
|
.hw.init = _fn(_name, _parent, \
|
|
&sprd_div_ops, _flags), \
|
|
} \
|
|
}
|
|
|
|
#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
|
|
_shift, _width, _flags) \
|
|
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
|
_shift, _width, _flags, CLK_HW_INIT)
|
|
|
|
#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
|
|
_shift, _width, _flags) \
|
|
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
|
_shift, _width, _flags, CLK_HW_INIT_HW)
|
|
|
|
static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
|
|
{
|
|
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
|
|
|
|
return container_of(common, struct sprd_div, common);
|
|
}
|
|
|
|
long sprd_div_helper_round_rate(struct sprd_clk_common *common,
|
|
const struct sprd_div_internal *div,
|
|
unsigned long rate,
|
|
unsigned long *parent_rate);
|
|
|
|
unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common,
|
|
const struct sprd_div_internal *div,
|
|
unsigned long parent_rate);
|
|
|
|
int sprd_div_helper_set_rate(const struct sprd_clk_common *common,
|
|
const struct sprd_div_internal *div,
|
|
unsigned long rate,
|
|
unsigned long parent_rate);
|
|
|
|
extern const struct clk_ops sprd_div_ops;
|
|
|
|
#endif /* _SPRD_DIV_H_ */
|