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b388f15fd1
This was found when using pwm-led on am33xx and enable heartbeat trigger. [ 808.624876] ================================= [ 808.629443] [ INFO: inconsistent lock state ] [ 808.634021] 3.9.0 #2 Not tainted [ 808.637415] --------------------------------- [ 808.641981] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage. [ 808.648288] swapper/0 [HC0[0]:SC1[1]:HE1:SE0] takes: [ 808.653494] (prepare_lock){+.?.+.}, at: [<c027c211>] clk_unprepare+0x15/0x24 [ 808.661040] {SOFTIRQ-ON-W} state was registered at: [ 808.666155] [<c004ec4d>] __lock_acquire+0x411/0x824 [ 808.671465] [<c004f359>] lock_acquire+0x41/0x50 [ 808.676412] [<c039ee9d>] mutex_lock_nested+0x31/0x1d8 [ 808.681912] [<c027c275>] clk_prepare+0x15/0x28 [ 808.686764] [<c0590c6b>] _init+0x117/0x1e0 [ 808.691256] [<c0019ef9>] omap_hwmod_for_each+0x29/0x3c [ 808.696842] [<c0591107>] __omap_hwmod_setup_all+0x17/0x2c [ 808.702696] [<c0008653>] do_one_initcall+0xc3/0x10c [ 808.708017] [<c058a627>] kernel_init_freeable+0xa7/0x134 [ 808.713778] [<c039a543>] kernel_init+0x7/0x98 [ 808.718544] [<c000cd95>] ret_from_fork+0x11/0x3c [ 808.723583] irq event stamp: 1379172 [ 808.727328] hardirqs last enabled at (1379172): [<c03a0759>] _raw_spin_unlock_irqrestore+0x21/0x30 [ 808.736828] hardirqs last disabled at (1379171): [<c03a03c3>] _raw_spin_lock_irqsave+0x13/0x38 [ 808.745876] softirqs last enabled at (1379164): [<c002ae5d>] irq_enter+0x49/0x4c [ 808.753747] softirqs last disabled at (1379165): [<c002aec3>] irq_exit+0x63/0x88 [ 808.761518] [ 808.761518] other info that might help us debug this: [ 808.768373] Possible unsafe locking scenario: [ 808.768373] [ 808.774578] CPU0 [ 808.777141] ---- [ 808.779705] lock(prepare_lock); [ 808.783186] <Interrupt> [ 808.785929] lock(prepare_lock); [ 808.789595] [ 808.789595] *** DEADLOCK *** [ 808.789595] [ 808.795805] 1 lock held by swapper/0: [ 808.799643] #0: (((&heartbeat_data->timer))){+.-...}, at: [<c002e204>] call_timer_fn+0x0/0x90 [ 808.808814] [ 808.808814] stack backtrace: [ 808.813402] [<c000ff19>] (unwind_backtrace+0x1/0x98) from [<c039bd75>] (print_usage_bug.part.25+0x16d/0x1cc) [ 808.823721] [<c039bd75>] (print_usage_bug.part.25+0x16d/0x1cc) from [<c004e595>] (mark_lock+0x18d/0x434) [ 808.833669] [<c004e595>] (mark_lock+0x18d/0x434) from [<c004ec1d>] (__lock_acquire+0x3e1/0x824) [ 808.842803] [<c004ec1d>] (__lock_acquire+0x3e1/0x824) from [<c004f359>] (lock_acquire+0x41/0x50) [ 808.852031] [<c004f359>] (lock_acquire+0x41/0x50) from [<c039ee9d>] (mutex_lock_nested+0x31/0x1d8) [ 808.861433] [<c039ee9d>] (mutex_lock_nested+0x31/0x1d8) from [<c027c211>] (clk_unprepare+0x15/0x24) [ 808.870930] [<c027c211>] (clk_unprepare+0x15/0x24) from [<c019f7bf>] (ehrpwm_pwm_disable+0x5f/0x80) [ 808.880431] [<c019f7bf>] (ehrpwm_pwm_disable+0x5f/0x80) from [<c019f29f>] (pwm_disable+0x27/0x28) [ 808.889751] [<c019f29f>] (pwm_disable+0x27/0x28) from [<c026f8f3>] (led_heartbeat_function+0x3f/0xb0) [ 808.899431] [<c026f8f3>] (led_heartbeat_function+0x3f/0xb0) from [<c002e249>] (call_timer_fn+0x45/0x90) [ 808.909288] [<c002e249>] (call_timer_fn+0x45/0x90) from [<c002e399>] (run_timer_softirq+0x105/0x17c) [ 808.918884] [<c002e399>] (run_timer_softirq+0x105/0x17c) from [<c002abc5>] (__do_softirq+0xa5/0x150) [ 808.928486] [<c002abc5>] (__do_softirq+0xa5/0x150) from [<c002aec3>] (irq_exit+0x63/0x88) [ 808.937098] [<c002aec3>] (irq_exit+0x63/0x88) from [<c000d599>] (handle_IRQ+0x21/0x54) [ 808.945415] [<c000d599>] (handle_IRQ+0x21/0x54) from [<c0008495>] (omap3_intc_handle_irq+0x5d/0x68) [ 808.954900] [<c0008495>] (omap3_intc_handle_irq+0x5d/0x68) from [<c000c7ff>] (__irq_svc+0x3f/0x64) [ 808.964287] Exception stack(0xc05b1f68 to 0xc05b1fb0) [ 808.969587] 1f60: 00000001 00000001 00000000 00000000 c05b0000 c0619748 [ 808.978158] 1f80: c05b0000 c05b0000 c0619748 413fc082 00000000 00000000 01000000 c05b1fb0 [ 808.986719] 1fa0: c004f989 c000d6f0 400f0033 ffffffff [ 808.992024] [<c000c7ff>] (__irq_svc+0x3f/0x64) from [<c000d6f0>] (cpu_idle+0x60/0x98) [ 809.000250] [<c000d6f0>] (cpu_idle+0x60/0x98) from [<c058a535>] (start_kernel+0x1e9/0x234) Remove non atomic clk api calls and use only atomic for enable/disable because can be called from atomic context (led_heartbeat_function is timer callback). Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
623 lines
16 KiB
C
623 lines
16 KiB
C
/*
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* EHRPWM PWM driver
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*
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* Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include "pwm-tipwmss.h"
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/* EHRPWM registers and bits definitions */
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/* Time base module registers */
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#define TBCTL 0x00
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#define TBPRD 0x0A
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#define TBCTL_RUN_MASK (BIT(15) | BIT(14))
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#define TBCTL_STOP_NEXT 0
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#define TBCTL_STOP_ON_CYCLE BIT(14)
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#define TBCTL_FREE_RUN (BIT(15) | BIT(14))
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#define TBCTL_PRDLD_MASK BIT(3)
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#define TBCTL_PRDLD_SHDW 0
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#define TBCTL_PRDLD_IMDT BIT(3)
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#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
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BIT(8) | BIT(7))
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#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
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#define TBCTL_CTRMODE_UP 0
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#define TBCTL_CTRMODE_DOWN BIT(0)
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#define TBCTL_CTRMODE_UPDOWN BIT(1)
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#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
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#define TBCTL_HSPCLKDIV_SHIFT 7
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#define TBCTL_CLKDIV_SHIFT 10
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#define CLKDIV_MAX 7
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#define HSPCLKDIV_MAX 7
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#define PERIOD_MAX 0xFFFF
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/* compare module registers */
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#define CMPA 0x12
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#define CMPB 0x14
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/* Action qualifier module registers */
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#define AQCTLA 0x16
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#define AQCTLB 0x18
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#define AQSFRC 0x1A
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#define AQCSFRC 0x1C
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#define AQCTL_CBU_MASK (BIT(9) | BIT(8))
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#define AQCTL_CBU_FRCLOW BIT(8)
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#define AQCTL_CBU_FRCHIGH BIT(9)
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#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
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#define AQCTL_CAU_MASK (BIT(5) | BIT(4))
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#define AQCTL_CAU_FRCLOW BIT(4)
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#define AQCTL_CAU_FRCHIGH BIT(5)
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#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
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#define AQCTL_PRD_MASK (BIT(3) | BIT(2))
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#define AQCTL_PRD_FRCLOW BIT(2)
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#define AQCTL_PRD_FRCHIGH BIT(3)
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#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
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#define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
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#define AQCTL_ZRO_FRCLOW BIT(0)
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#define AQCTL_ZRO_FRCHIGH BIT(1)
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#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
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#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
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AQCTL_ZRO_FRCHIGH)
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#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
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AQCTL_ZRO_FRCLOW)
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#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
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AQCTL_ZRO_FRCHIGH)
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#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
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AQCTL_ZRO_FRCLOW)
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#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
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#define AQSFRC_RLDCSF_ZRO 0
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#define AQSFRC_RLDCSF_PRD BIT(6)
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#define AQSFRC_RLDCSF_ZROPRD BIT(7)
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#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
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#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
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#define AQCSFRC_CSFB_FRCDIS 0
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#define AQCSFRC_CSFB_FRCLOW BIT(2)
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#define AQCSFRC_CSFB_FRCHIGH BIT(3)
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#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
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#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
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#define AQCSFRC_CSFA_FRCDIS 0
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#define AQCSFRC_CSFA_FRCLOW BIT(0)
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#define AQCSFRC_CSFA_FRCHIGH BIT(1)
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#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
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#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
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struct ehrpwm_context {
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u16 tbctl;
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u16 tbprd;
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u16 cmpa;
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u16 cmpb;
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u16 aqctla;
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u16 aqctlb;
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u16 aqsfrc;
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u16 aqcsfrc;
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};
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struct ehrpwm_pwm_chip {
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struct pwm_chip chip;
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unsigned int clk_rate;
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void __iomem *mmio_base;
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unsigned long period_cycles[NUM_PWM_CHANNEL];
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enum pwm_polarity polarity[NUM_PWM_CHANNEL];
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struct clk *tbclk;
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struct ehrpwm_context ctx;
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};
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static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct ehrpwm_pwm_chip, chip);
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}
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static u16 ehrpwm_read(void *base, int offset)
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{
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return readw(base + offset);
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}
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static void ehrpwm_write(void *base, int offset, unsigned int val)
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{
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writew(val & 0xFFFF, base + offset);
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}
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static void ehrpwm_modify(void *base, int offset,
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unsigned short mask, unsigned short val)
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{
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unsigned short regval;
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regval = readw(base + offset);
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regval &= ~mask;
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regval |= val & mask;
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writew(regval, base + offset);
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}
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/**
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* set_prescale_div - Set up the prescaler divider function
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* @rqst_prescaler: prescaler value min
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* @prescale_div: prescaler value set
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* @tb_clk_div: Time Base Control prescaler bits
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*/
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static int set_prescale_div(unsigned long rqst_prescaler,
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unsigned short *prescale_div, unsigned short *tb_clk_div)
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{
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unsigned int clkdiv, hspclkdiv;
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for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
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for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
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/*
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* calculations for prescaler value :
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* prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
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* HSPCLKDIVIDER = 2 ** hspclkdiv
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* CLKDIVIDER = (1), if clkdiv == 0 *OR*
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* (2 * clkdiv), if clkdiv != 0
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*
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* Configure prescale_div value such that period
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* register value is less than 65535.
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*/
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*prescale_div = (1 << clkdiv) *
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(hspclkdiv ? (hspclkdiv * 2) : 1);
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if (*prescale_div > rqst_prescaler) {
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*tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
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(hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
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return 0;
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}
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}
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}
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return 1;
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}
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static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)
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{
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int aqctl_reg;
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unsigned short aqctl_val, aqctl_mask;
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/*
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* Configure PWM output to HIGH/LOW level on counter
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* reaches compare register value and LOW/HIGH level
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* on counter value reaches period register value and
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* zero value on counter
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*/
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if (chan == 1) {
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aqctl_reg = AQCTLB;
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aqctl_mask = AQCTL_CBU_MASK;
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if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
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aqctl_val = AQCTL_CHANB_POLINVERSED;
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else
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aqctl_val = AQCTL_CHANB_POLNORMAL;
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} else {
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aqctl_reg = AQCTLA;
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aqctl_mask = AQCTL_CAU_MASK;
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if (pc->polarity[chan] == PWM_POLARITY_INVERSED)
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aqctl_val = AQCTL_CHANA_POLINVERSED;
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else
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aqctl_val = AQCTL_CHANA_POLNORMAL;
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}
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aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
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ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
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}
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/*
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* period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
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* duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
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*/
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static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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unsigned long long c;
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unsigned long period_cycles, duty_cycles;
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unsigned short ps_divval, tb_divval;
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int i, cmp_reg;
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if (period_ns > NSEC_PER_SEC)
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return -ERANGE;
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c = pc->clk_rate;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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period_cycles = (unsigned long)c;
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if (period_cycles < 1) {
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period_cycles = 1;
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duty_cycles = 1;
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} else {
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c = pc->clk_rate;
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c = c * duty_ns;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = (unsigned long)c;
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}
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/*
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* Period values should be same for multiple PWM channels as IP uses
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* same period register for multiple channels.
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*/
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for (i = 0; i < NUM_PWM_CHANNEL; i++) {
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if (pc->period_cycles[i] &&
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(pc->period_cycles[i] != period_cycles)) {
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/*
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* Allow channel to reconfigure period if no other
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* channels being configured.
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*/
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if (i == pwm->hwpwm)
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continue;
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dev_err(chip->dev, "Period value conflicts with channel %d\n",
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i);
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return -EINVAL;
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}
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}
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pc->period_cycles[pwm->hwpwm] = period_cycles;
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/* Configure clock prescaler to support Low frequency PWM wave */
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if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
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&tb_divval)) {
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dev_err(chip->dev, "Unsupported values\n");
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return -EINVAL;
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}
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pm_runtime_get_sync(chip->dev);
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/* Update clock prescaler values */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
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/* Update period & duty cycle with presacler division */
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period_cycles = period_cycles / ps_divval;
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duty_cycles = duty_cycles / ps_divval;
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/* Configure shadow loading on Period register */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
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ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
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/* Configure ehrpwm counter for up-count mode */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
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TBCTL_CTRMODE_UP);
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if (pwm->hwpwm == 1)
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/* Channel 1 configured with compare B register */
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cmp_reg = CMPB;
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else
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/* Channel 0 configured with compare A register */
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cmp_reg = CMPA;
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ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
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pm_runtime_put_sync(chip->dev);
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return 0;
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}
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static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm, enum pwm_polarity polarity)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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/* Configuration of polarity in hardware delayed, do at enable */
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pc->polarity[pwm->hwpwm] = polarity;
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return 0;
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}
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static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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unsigned short aqcsfrc_val, aqcsfrc_mask;
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int ret;
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/* Leave clock enabled on enabling PWM */
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pm_runtime_get_sync(chip->dev);
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/* Disabling Action Qualifier on PWM output */
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if (pwm->hwpwm) {
|
|
aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
|
|
aqcsfrc_mask = AQCSFRC_CSFB_MASK;
|
|
} else {
|
|
aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
|
|
aqcsfrc_mask = AQCSFRC_CSFA_MASK;
|
|
}
|
|
|
|
/* Changes to shadow mode */
|
|
ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
|
|
AQSFRC_RLDCSF_ZRO);
|
|
|
|
ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
|
|
|
|
/* Channels polarity can be configured from action qualifier module */
|
|
configure_polarity(pc, pwm->hwpwm);
|
|
|
|
/* Enable TBCLK before enabling PWM device */
|
|
ret = clk_enable(pc->tbclk);
|
|
if (ret) {
|
|
pr_err("Failed to enable TBCLK for %s\n",
|
|
dev_name(pc->chip.dev));
|
|
return ret;
|
|
}
|
|
|
|
/* Enable time counter for free_run */
|
|
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN);
|
|
return 0;
|
|
}
|
|
|
|
static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
|
{
|
|
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
|
|
unsigned short aqcsfrc_val, aqcsfrc_mask;
|
|
|
|
/* Action Qualifier puts PWM output low forcefully */
|
|
if (pwm->hwpwm) {
|
|
aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
|
|
aqcsfrc_mask = AQCSFRC_CSFB_MASK;
|
|
} else {
|
|
aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
|
|
aqcsfrc_mask = AQCSFRC_CSFA_MASK;
|
|
}
|
|
|
|
/*
|
|
* Changes to immediate action on Action Qualifier. This puts
|
|
* Action Qualifier control on PWM output from next TBCLK
|
|
*/
|
|
ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
|
|
AQSFRC_RLDCSF_IMDT);
|
|
|
|
ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
|
|
|
|
/* Disabling TBCLK on PWM disable */
|
|
clk_disable(pc->tbclk);
|
|
|
|
/* Stop Time base counter */
|
|
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT);
|
|
|
|
/* Disable clock on PWM disable */
|
|
pm_runtime_put_sync(chip->dev);
|
|
}
|
|
|
|
static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
|
{
|
|
struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
|
|
|
|
if (test_bit(PWMF_ENABLED, &pwm->flags)) {
|
|
dev_warn(chip->dev, "Removing PWM device without disabling\n");
|
|
pm_runtime_put_sync(chip->dev);
|
|
}
|
|
|
|
/* set period value to zero on free */
|
|
pc->period_cycles[pwm->hwpwm] = 0;
|
|
}
|
|
|
|
static const struct pwm_ops ehrpwm_pwm_ops = {
|
|
.free = ehrpwm_pwm_free,
|
|
.config = ehrpwm_pwm_config,
|
|
.set_polarity = ehrpwm_pwm_set_polarity,
|
|
.enable = ehrpwm_pwm_enable,
|
|
.disable = ehrpwm_pwm_disable,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static const struct of_device_id ehrpwm_of_match[] = {
|
|
{ .compatible = "ti,am33xx-ehrpwm" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ehrpwm_of_match);
|
|
|
|
static int ehrpwm_pwm_probe(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
struct resource *r;
|
|
struct clk *clk;
|
|
struct ehrpwm_pwm_chip *pc;
|
|
u16 status;
|
|
struct pinctrl *pinctrl;
|
|
|
|
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
if (IS_ERR(pinctrl))
|
|
dev_warn(&pdev->dev, "unable to select pin group\n");
|
|
|
|
pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
|
|
if (!pc) {
|
|
dev_err(&pdev->dev, "failed to allocate memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
clk = devm_clk_get(&pdev->dev, "fck");
|
|
if (IS_ERR(clk)) {
|
|
dev_err(&pdev->dev, "failed to get clock\n");
|
|
return PTR_ERR(clk);
|
|
}
|
|
|
|
pc->clk_rate = clk_get_rate(clk);
|
|
if (!pc->clk_rate) {
|
|
dev_err(&pdev->dev, "failed to get clock rate\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pc->chip.dev = &pdev->dev;
|
|
pc->chip.ops = &ehrpwm_pwm_ops;
|
|
pc->chip.of_xlate = of_pwm_xlate_with_flags;
|
|
pc->chip.of_pwm_n_cells = 3;
|
|
pc->chip.base = -1;
|
|
pc->chip.npwm = NUM_PWM_CHANNEL;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
|
|
if (IS_ERR(pc->mmio_base))
|
|
return PTR_ERR(pc->mmio_base);
|
|
|
|
/* Acquire tbclk for Time Base EHRPWM submodule */
|
|
pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");
|
|
if (IS_ERR(pc->tbclk)) {
|
|
dev_err(&pdev->dev, "Failed to get tbclk\n");
|
|
return PTR_ERR(pc->tbclk);
|
|
}
|
|
|
|
ret = clk_prepare(pc->tbclk);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "clk_prepare() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = pwmchip_add(&pc->chip);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
status = pwmss_submodule_state_change(pdev->dev.parent,
|
|
PWMSS_EPWMCLK_EN);
|
|
if (!(status & PWMSS_EPWMCLK_EN_ACK)) {
|
|
dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
|
|
ret = -EINVAL;
|
|
goto pwmss_clk_failure;
|
|
}
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
platform_set_drvdata(pdev, pc);
|
|
return 0;
|
|
|
|
pwmss_clk_failure:
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pwmchip_remove(&pc->chip);
|
|
clk_unprepare(pc->tbclk);
|
|
return ret;
|
|
}
|
|
|
|
static int ehrpwm_pwm_remove(struct platform_device *pdev)
|
|
{
|
|
struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
|
|
|
|
clk_unprepare(pc->tbclk);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
/*
|
|
* Due to hardware misbehaviour, acknowledge of the stop_req
|
|
* is missing. Hence checking of the status bit skipped.
|
|
*/
|
|
pwmss_submodule_state_change(pdev->dev.parent, PWMSS_EPWMCLK_STOP_REQ);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return pwmchip_remove(&pc->chip);
|
|
}
|
|
|
|
static void ehrpwm_pwm_save_context(struct ehrpwm_pwm_chip *pc)
|
|
{
|
|
pm_runtime_get_sync(pc->chip.dev);
|
|
pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);
|
|
pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);
|
|
pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);
|
|
pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);
|
|
pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);
|
|
pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);
|
|
pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);
|
|
pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);
|
|
pm_runtime_put_sync(pc->chip.dev);
|
|
}
|
|
|
|
static void ehrpwm_pwm_restore_context(struct ehrpwm_pwm_chip *pc)
|
|
{
|
|
ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);
|
|
ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);
|
|
ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);
|
|
ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);
|
|
ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);
|
|
ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);
|
|
ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);
|
|
ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int ehrpwm_pwm_suspend(struct device *dev)
|
|
{
|
|
struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
ehrpwm_pwm_save_context(pc);
|
|
for (i = 0; i < pc->chip.npwm; i++) {
|
|
struct pwm_device *pwm = &pc->chip.pwms[i];
|
|
|
|
if (!test_bit(PWMF_ENABLED, &pwm->flags))
|
|
continue;
|
|
|
|
/* Disable explicitly if PWM is running */
|
|
pm_runtime_put_sync(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int ehrpwm_pwm_resume(struct device *dev)
|
|
{
|
|
struct ehrpwm_pwm_chip *pc = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < pc->chip.npwm; i++) {
|
|
struct pwm_device *pwm = &pc->chip.pwms[i];
|
|
|
|
if (!test_bit(PWMF_ENABLED, &pwm->flags))
|
|
continue;
|
|
|
|
/* Enable explicitly if PWM was running */
|
|
pm_runtime_get_sync(dev);
|
|
}
|
|
ehrpwm_pwm_restore_context(pc);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(ehrpwm_pwm_pm_ops, ehrpwm_pwm_suspend,
|
|
ehrpwm_pwm_resume);
|
|
|
|
static struct platform_driver ehrpwm_pwm_driver = {
|
|
.driver = {
|
|
.name = "ehrpwm",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = ehrpwm_of_match,
|
|
.pm = &ehrpwm_pwm_pm_ops,
|
|
},
|
|
.probe = ehrpwm_pwm_probe,
|
|
.remove = ehrpwm_pwm_remove,
|
|
};
|
|
|
|
module_platform_driver(ehrpwm_pwm_driver);
|
|
|
|
MODULE_DESCRIPTION("EHRPWM PWM driver");
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
MODULE_LICENSE("GPL");
|