Dhaval Shah cee8113a29 soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver ... Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2018-01-08 13:42:47 +01:00
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actions	soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating	2017-06-23 17:43:27 +02:00
amlogic	soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader	2017-11-09 11:42:17 +01:00
atmel	drivers: soc: atmel: Add basic support for new sama5d2 SiPs	2017-09-17 19:45:59 +02:00
bcm	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
dove	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
fsl	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
imx	soc: imx: gpcv2: fix regulator deferred probe	2017-08-05 11:12:20 +08:00
lantiq	MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd	2017-09-04 21:19:02 +02:00
mediatek	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
qcom	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
renesas	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
rockchip	soc: rockchip: power-domain: Use GENPD_FLAG_ACTIVE_WAKEUP	2017-11-08 01:00:47 +01:00
samsung	soc: samsung: Remove Exynos4212 related dead code	2017-10-08 14:17:13 +02:00
sunxi	drivers: soc: sunxi: add support for A64 and its SRAM C	2017-08-18 14:30:21 +08:00
tegra	ARM: SoC driver updates for v4.15	2017-11-16 16:05:01 -08:00
ti	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
ux500	ARM: ux500: move soc_id driver to drivers/soc	2016-07-12 11:24:09 +02:00
versatile	soc: versatile: remove unnecessary static in realview_soc_probe()	2017-08-16 22:28:27 +02:00
xilinx	soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver	2018-01-08 13:42:47 +01:00
zte	soc: zte: Restrict SOC_ZTE to ARCH_ZX or COMPILE_TEST	2017-07-27 13:12:34 +02:00
Kconfig	soc: xilinx: Create folder structure for soc specific drivers	2018-01-08 13:42:39 +01:00
Makefile	soc: xilinx: Create folder structure for soc specific drivers	2018-01-08 13:42:39 +01:00