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da81593a5a
Some later changes in cpufreq core require these tables to be sorted based on ascending order of their frequencies. There was only one offender. Fix it and add comments over the arrays. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
98 lines
3.8 KiB
C
98 lines
3.8 KiB
C
/*
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* Copyright (c) 2006-2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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* Vincent Sanders <vince@arm.linux.org.uk>
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*
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* S3C2410 CPU PLL tables
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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/* This array should be sorted in ascending order of the frequencies */
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static struct cpufreq_frequency_table pll_vals_12MHz[] = {
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{ .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
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{ .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
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{ .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
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{ .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
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{ .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
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{ .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
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{ .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },
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{ .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), },
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{ .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), },
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{ .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), },
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{ .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), },
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{ .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), },
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{ .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), },
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{ .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), },
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{ .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), },
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{ .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), },
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{ .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), },
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{ .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), },
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{ .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), },
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{ .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), },
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{ .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), },
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{ .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), },
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/* 2410A extras */
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{ .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), },
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{ .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), },
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{ .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), },
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{ .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), },
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{ .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), },
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};
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static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
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{
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return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
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}
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static struct subsys_interface s3c2410_plls_interface = {
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.name = "s3c2410_plls",
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.subsys = &s3c2410_subsys,
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.add_dev = s3c2410_plls_add,
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};
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static int __init s3c2410_pll_init(void)
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{
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return subsys_interface_register(&s3c2410_plls_interface);
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}
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arch_initcall(s3c2410_pll_init);
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static struct subsys_interface s3c2410a_plls_interface = {
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.name = "s3c2410a_plls",
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.subsys = &s3c2410a_subsys,
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.add_dev = s3c2410_plls_add,
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};
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static int __init s3c2410a_pll_init(void)
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{
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return subsys_interface_register(&s3c2410a_plls_interface);
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}
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arch_initcall(s3c2410a_pll_init);
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