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cdedef59de
This patch configures the VSIs to be able to send and receive packets by doing the following: 1) Initialize flexible parser to extract and include certain fields in the Rx descriptor. 2) Add Tx queues by programming the Tx queue context (implemented in ice_vsi_cfg_txqs). Note that adding the queues also enables (starts) the queues. 3) Add Rx queues by programming Rx queue context (implemented in ice_vsi_cfg_rxqs). Note that this only adds queues but doesn't start them. The rings will be started by calling ice_vsi_start_rx_rings on interface up. 4) Configure interrupts for VSI queues. 5) Implement ice_open and ice_stop. Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Tony Brelinski <tonyx.brelinski@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
185 lines
8.5 KiB
C
185 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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/* Machine-generated file */
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#ifndef _ICE_HW_AUTOGEN_H_
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#define _ICE_HW_AUTOGEN_H_
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#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
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#define PF_FW_ARQBAH 0x00080180
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#define PF_FW_ARQBAL 0x00080080
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#define PF_FW_ARQH 0x00080380
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#define PF_FW_ARQH_ARQH_S 0
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#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, PF_FW_ARQH_ARQH_S)
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#define PF_FW_ARQLEN 0x00080280
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#define PF_FW_ARQLEN_ARQLEN_S 0
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#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, PF_FW_ARQLEN_ARQLEN_S)
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#define PF_FW_ARQLEN_ARQVFE_S 28
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#define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)
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#define PF_FW_ARQLEN_ARQOVFL_S 29
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#define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S)
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#define PF_FW_ARQLEN_ARQCRIT_S 30
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#define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S)
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#define PF_FW_ARQLEN_ARQENABLE_S 31
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#define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)
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#define PF_FW_ARQT 0x00080480
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#define PF_FW_ATQBAH 0x00080100
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#define PF_FW_ATQBAL 0x00080000
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#define PF_FW_ATQH 0x00080300
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#define PF_FW_ATQH_ATQH_S 0
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#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, PF_FW_ATQH_ATQH_S)
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#define PF_FW_ATQLEN 0x00080200
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#define PF_FW_ATQLEN_ATQLEN_S 0
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#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
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#define PF_FW_ATQLEN_ATQVFE_S 28
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#define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)
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#define PF_FW_ATQLEN_ATQOVFL_S 29
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#define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S)
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#define PF_FW_ATQLEN_ATQCRIT_S 30
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#define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S)
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#define PF_FW_ATQLEN_ATQENABLE_S 31
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#define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)
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#define PF_FW_ATQT 0x00080400
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#define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256))
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S)
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S)
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24
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#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S)
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#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
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#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
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#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S)
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#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
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#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S)
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#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
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#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
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#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S)
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#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
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#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S)
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#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
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#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
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#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S)
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#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
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#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S)
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#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
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#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
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#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S)
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#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
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#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S)
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#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
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#define QRXFLXP_CNTXT_RXDID_IDX_S 0
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#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, QRXFLXP_CNTXT_RXDID_IDX_S)
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#define QRXFLXP_CNTXT_RXDID_PRIO_S 8
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#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, QRXFLXP_CNTXT_RXDID_PRIO_S)
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#define QRXFLXP_CNTXT_TS_S 11
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#define QRXFLXP_CNTXT_TS_M BIT(QRXFLXP_CNTXT_TS_S)
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#define GLGEN_RSTAT 0x000B8188
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#define GLGEN_RSTAT_DEVSTATE_S 0
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#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, GLGEN_RSTAT_DEVSTATE_S)
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#define GLGEN_RSTCTL 0x000B8180
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#define GLGEN_RSTCTL_GRSTDEL_S 0
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#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
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#define GLGEN_RTRIG 0x000B8190
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#define GLGEN_RTRIG_CORER_S 0
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#define GLGEN_RTRIG_CORER_M BIT(GLGEN_RTRIG_CORER_S)
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#define GLGEN_RTRIG_GLOBR_S 1
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#define GLGEN_RTRIG_GLOBR_M BIT(GLGEN_RTRIG_GLOBR_S)
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#define GLGEN_STAT 0x000B612C
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#define PFGEN_CTRL 0x00091000
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#define PFGEN_CTRL_PFSWR_S 0
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#define PFGEN_CTRL_PFSWR_M BIT(PFGEN_CTRL_PFSWR_S)
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#define PFHMC_ERRORDATA 0x00520500
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#define PFHMC_ERRORINFO 0x00520400
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#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
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#define GLINT_DYN_CTL_INTENA_S 0
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#define GLINT_DYN_CTL_INTENA_M BIT(GLINT_DYN_CTL_INTENA_S)
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#define GLINT_DYN_CTL_CLEARPBA_S 1
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#define GLINT_DYN_CTL_CLEARPBA_M BIT(GLINT_DYN_CTL_CLEARPBA_S)
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#define GLINT_DYN_CTL_SWINT_TRIG_S 2
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#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(GLINT_DYN_CTL_SWINT_TRIG_S)
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#define GLINT_DYN_CTL_ITR_INDX_S 3
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#define GLINT_DYN_CTL_SW_ITR_INDX_S 25
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#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, GLINT_DYN_CTL_SW_ITR_INDX_S)
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#define GLINT_DYN_CTL_INTENA_MSK_S 31
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#define GLINT_DYN_CTL_INTENA_MSK_M BIT(GLINT_DYN_CTL_INTENA_MSK_S)
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#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
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#define PFINT_FW_CTL 0x0016C800
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#define PFINT_FW_CTL_MSIX_INDX_S 0
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#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, PFINT_FW_CTL_MSIX_INDX_S)
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#define PFINT_FW_CTL_ITR_INDX_S 11
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#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, PFINT_FW_CTL_ITR_INDX_S)
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#define PFINT_FW_CTL_CAUSE_ENA_S 30
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#define PFINT_FW_CTL_CAUSE_ENA_M BIT(PFINT_FW_CTL_CAUSE_ENA_S)
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#define PFINT_OICR 0x0016CA00
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#define PFINT_OICR_INTEVENT_S 0
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#define PFINT_OICR_INTEVENT_M BIT(PFINT_OICR_INTEVENT_S)
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#define PFINT_OICR_HLP_RDY_S 14
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#define PFINT_OICR_HLP_RDY_M BIT(PFINT_OICR_HLP_RDY_S)
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#define PFINT_OICR_CPM_RDY_S 15
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#define PFINT_OICR_CPM_RDY_M BIT(PFINT_OICR_CPM_RDY_S)
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#define PFINT_OICR_ECC_ERR_S 16
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#define PFINT_OICR_ECC_ERR_M BIT(PFINT_OICR_ECC_ERR_S)
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#define PFINT_OICR_MAL_DETECT_S 19
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#define PFINT_OICR_MAL_DETECT_M BIT(PFINT_OICR_MAL_DETECT_S)
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#define PFINT_OICR_GRST_S 20
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#define PFINT_OICR_GRST_M BIT(PFINT_OICR_GRST_S)
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#define PFINT_OICR_PCI_EXCEPTION_S 21
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#define PFINT_OICR_PCI_EXCEPTION_M BIT(PFINT_OICR_PCI_EXCEPTION_S)
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#define PFINT_OICR_GPIO_S 22
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#define PFINT_OICR_GPIO_M BIT(PFINT_OICR_GPIO_S)
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#define PFINT_OICR_STORM_DETECT_S 24
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#define PFINT_OICR_STORM_DETECT_M BIT(PFINT_OICR_STORM_DETECT_S)
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#define PFINT_OICR_HMC_ERR_S 26
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#define PFINT_OICR_HMC_ERR_M BIT(PFINT_OICR_HMC_ERR_S)
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#define PFINT_OICR_PE_CRITERR_S 28
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#define PFINT_OICR_PE_CRITERR_M BIT(PFINT_OICR_PE_CRITERR_S)
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#define PFINT_OICR_CTL 0x0016CA80
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#define PFINT_OICR_CTL_MSIX_INDX_S 0
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#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, PFINT_OICR_CTL_MSIX_INDX_S)
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#define PFINT_OICR_CTL_ITR_INDX_S 11
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#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, PFINT_OICR_CTL_ITR_INDX_S)
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#define PFINT_OICR_CTL_CAUSE_ENA_S 30
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#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(PFINT_OICR_CTL_CAUSE_ENA_S)
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#define PFINT_OICR_ENA 0x0016C900
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#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
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#define QINT_RQCTL_MSIX_INDX_S 0
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#define QINT_RQCTL_ITR_INDX_S 11
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#define QINT_RQCTL_CAUSE_ENA_S 30
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#define QINT_RQCTL_CAUSE_ENA_M BIT(QINT_RQCTL_CAUSE_ENA_S)
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#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
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#define QINT_TQCTL_MSIX_INDX_S 0
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#define QINT_TQCTL_ITR_INDX_S 11
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#define QINT_TQCTL_CAUSE_ENA_S 30
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#define QINT_TQCTL_CAUSE_ENA_M BIT(QINT_TQCTL_CAUSE_ENA_S)
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#define GLLAN_RCTL_0 0x002941F8
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#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
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#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
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#define QRX_CTRL_MAX_INDEX 2047
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#define QRX_CTRL_QENA_REQ_S 0
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#define QRX_CTRL_QENA_REQ_M BIT(QRX_CTRL_QENA_REQ_S)
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#define QRX_CTRL_QENA_STAT_S 2
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#define QRX_CTRL_QENA_STAT_M BIT(QRX_CTRL_QENA_STAT_S)
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#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
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#define GLNVM_FLA 0x000B6108
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#define GLNVM_FLA_LOCKED_S 6
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#define GLNVM_FLA_LOCKED_M BIT(GLNVM_FLA_LOCKED_S)
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#define GLNVM_GENS 0x000B6100
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#define GLNVM_GENS_SR_SIZE_S 5
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#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, GLNVM_GENS_SR_SIZE_S)
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#define GLNVM_ULD 0x000B6008
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#define GLNVM_ULD_CORER_DONE_S 3
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#define GLNVM_ULD_CORER_DONE_M BIT(GLNVM_ULD_CORER_DONE_S)
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#define GLNVM_ULD_GLOBR_DONE_S 4
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#define GLNVM_ULD_GLOBR_DONE_M BIT(GLNVM_ULD_GLOBR_DONE_S)
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#define PF_FUNC_RID 0x0009E880
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#define PF_FUNC_RID_FUNC_NUM_S 0
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#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, PF_FUNC_RID_FUNC_NUM_S)
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#endif /* _ICE_HW_AUTOGEN_H_ */
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