Andrzej Hajda cdb68fbd4e clk: samsung: exynos5260: Fix PLL rates ... Rates declared in PLL rate tables should match exactly rates calculated from the PLL coefficients. If that is not the case, rate of the PLL's child clock might be set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is, the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by the PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>		2018-02-23 15:15:01 +01:00
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at91	clk: at91: pmc: Support backup for programmable clocks	2017-12-21 16:34:06 -08:00
axis	clk: axis: Use new macro CLK_OF_DECLARE_DRIVER	2016-08-12 18:00:37 -07:00
axs10x	clk: axs10x: introduce AXS10X pll driver	2017-07-17 11:50:59 -07:00
bcm	clk: iproc: Minor tidy up of iproc pll data structures	2017-12-28 14:53:37 -08:00
berlin	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
h8300	clk: h8300: pr_err() strings should end with newlines	2017-12-06 22:40:02 -08:00
hisilicon	Merge branch 'clk-divider-container' into clk-next	2018-01-26 16:43:14 -08:00
imgtec	Update MIPS email addresses	2017-11-03 09:02:30 -07:00
imx	clk: imx51: uart4, uart5 gates only exist on imx50, imx53	2017-12-21 15:59:05 -08:00
ingenic	clk: Add Ingenic jz4770 CGU driver	2018-01-18 22:05:55 +00:00
keystone	clk: keystone: sci-clk: Fix sci_clk_get	2017-08-02 18:37:26 -07:00
loongson1	CLK: Add Loongson1C clock support	2016-09-23 14:49:21 -07:00
mediatek	clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built	2018-01-10 13:41:15 -08:00
meson	clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()	2018-01-10 13:24:36 -08:00
microchip	clk: microchip: Initialize SOSC clock rate for PIC32MZDA.	2016-08-24 16:05:24 -07:00
mmp	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
mvebu	Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-next	2018-01-26 16:41:58 -08:00
mxs	clk: mxs: make clk_ops const	2017-11-01 23:25:43 -07:00
nxp	Merge branch 'clk-divider-container' into clk-next	2018-01-26 16:43:14 -08:00
pistachio
pxa	clk: pxa: unbreak lookup of CLK_POUT	2017-12-28 10:43:30 -08:00
qcom	Merge branch 'clk-divider-container' into clk-next	2018-01-26 16:43:14 -08:00
renesas	clk: renesas: r8a7796: Add FDP clock	2018-01-05 11:14:38 +01:00
rockchip	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
samsung	clk: samsung: exynos5260: Fix PLL rates	2018-02-23 15:15:01 +01:00
sirf	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
socfpga	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
spear	SPEAr: clk: pr_err() strings should end with newlines	2017-12-06 22:39:59 -08:00
sprd	Merge branch 'clk-divider-container' into clk-next	2018-01-26 16:43:14 -08:00
st	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
sunxi	The core framework has a handful of patches this time around, mostly due	2018-02-01 16:56:07 -08:00
sunxi-ng	Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into clk-next	2018-01-26 16:43:39 -08:00
tegra	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
ti	Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' and 'clk-omap' into clk-next	2018-01-26 16:41:39 -08:00
uniphier	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
ux500	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
versatile	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
x86	clk: x86: Do not gate clocks enabled by the firmware	2017-07-18 16:23:13 -07:00
zte	clk: move clock common macros out from vendor directories	2017-12-21 15:00:38 -08:00
zynq	clk: zynq: Remove CLK_IS_ROOT	2016-03-02 17:48:26 -08:00
clk-asm9260.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-aspeed.c	clk: aspeed: Handle inverse polarity of USB port 1 clock gate	2018-01-26 16:22:48 -08:00
clk-axi-clkgen.c	clk: axi-clkgen: Round closest in round_rate() and recalc_rate()	2017-12-21 18:07:53 -08:00
clk-axm5516.c	clk: axm5516: Migrate to clk_hw based OF and registration APIs	2016-08-24 16:11:07 -07:00
clk-bulk.c	clk: Export clk_bulk_prepare()	2017-09-29 14:17:17 -07:00
clk-cdce706.c	clk: cdce: Migrate to clk_hw based OF and registration APIs	2016-08-24 16:12:38 -07:00
clk-cdce925.c	clk: cdce925: remove redundant check for non-null parent_name	2017-11-13 17:44:15 -08:00
clk-clps711x.c	clk: clps711x: Migrate to clk_hw based OF and registration APIs	2016-08-24 17:19:26 -07:00
clk-composite.c	Merge branch 'clk-hw-register' (early part) into clk-next	2016-04-21 14:47:18 -07:00
clk-conf.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-cs2000-cp.c	clk: cs2000: Add cs2000_set_saved_rate	2017-08-31 11:32:32 -07:00
clk-devres.c	clk: add managed version of clk_bulk_get	2017-06-02 15:37:49 -07:00
clk-divider.c	clk: divider: fix incorrect usage of container_of	2017-12-28 15:16:04 -08:00
clk-efm32gg.c	clk: efm32gg: Pass correct type to hw provider registration	2016-11-16 11:08:55 -08:00
clk-fixed-factor.c	clk: fixed-factor: Remove export symbol on setup function	2016-08-15 15:08:03 -07:00
clk-fixed-rate.c	clk: fixed-rate: Remove export symbol on setup function	2016-08-15 15:08:06 -07:00
clk-fractional-divider.c	clk: fractional-divider: allow overriding of approximation	2017-08-08 17:39:48 +02:00
clk-gate.c	clk: gate: expose clk_gate_ops::is_enabled	2017-08-31 18:35:45 -07:00
clk-gemini.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
clk-gpio.c	clk: clk-gpio: Request GPIO descriptor as LOW	2017-11-02 01:20:40 -07:00
clk-hi655x.c	clk: hi6220: Add the hi655x's pmic clock	2017-04-21 19:18:53 -07:00
clk-highbank.c	clk: highbank: Migrate to clk_hw based registration and OF APIs	2016-06-30 12:25:28 -07:00
clk-hsdk-pll.c	ARC: clk: fix spelling mistake: "configurarion" -> "configuration"	2017-11-13 17:44:26 -08:00
clk-max77686.c	clk: max77686: fix number of clocks setup for clk_hw based registration	2016-10-17 15:31:59 -07:00
clk-moxart.c	clk: Convert to using %pOF instead of full_name	2017-07-21 15:49:54 -07:00
clk-multiplier.c	clk: multiplier: Prevent the multiplier from under / over flowing	2016-06-20 13:00:00 -07:00
clk-mux.c	clk: clk-mux: Improve a size determination in clk_hw_register_mux_table()	2017-11-13 17:28:39 -08:00
clk-nomadik.c	clk: nomadik: Delete error messages for a failed memory allocation in two functions	2017-04-21 19:47:14 -07:00
clk-nspire.c	clk: nspire: Migrate to clk_hw based OF and registration APIs	2016-08-24 17:23:21 -07:00
clk-oxnas.c	clk: oxnas: Add OX820 Gate clocks	2016-10-23 10:18:45 -07:00
clk-palmas.c	clk: palmas: undo preparation of a clock source.	2017-06-02 10:51:34 -07:00
clk-pwm.c	clk: pwm: Migrate to clk_hw based OF and registration APIs	2016-08-24 17:23:27 -07:00
clk-qoriq.c	clk: qoriq: add more divider clocks support	2017-12-21 15:57:28 -08:00
clk-rk808.c	clk: rk808: Pass the right pointer as the get_hw context	2016-09-09 11:07:07 -07:00
clk-s2mps11.c	clk: s2mps11: Migrate to clk_hw based OF and registration APIs	2016-06-30 12:29:14 -07:00
clk-scpi.c	clk: scpi: error when clock fails to register	2017-06-29 18:47:35 -07:00
clk-si514.c	clk: si514: Migrate to clk_hw based OF and registration APIs	2016-08-24 17:29:59 -07:00
clk-si570.c	clk: si570: Migrate to clk_hw based OF and registration APIs	2016-08-24 17:30:01 -07:00
clk-si5351.c	clk: si5351: _si5351_clkout_reset_pll() can be static	2017-12-28 10:49:48 -08:00
clk-si5351.h
clk-stm32f4.c	clk: stm32f4: pr_err() strings should end with newlines	2017-12-06 22:39:51 -08:00
clk-stm32h7.c	clk: stm32-h7: fix copyright	2017-12-06 23:07:34 -08:00
clk-tango4.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
clk-twl6040.c	clk: make clk_init_data const	2017-11-01 23:25:51 -07:00
clk-u300.c	clk: clk-u300: Fix a typo in two comment lines	2017-11-13 17:39:43 -08:00
clk-versaclock5.c	clk: vc5: Add support for IDT VersaClock 5P49V5925	2017-07-17 11:51:00 -07:00
clk-vt8500.c	clk: vt8500: Migrate to clk_hw based registration APIs	2016-08-24 17:35:48 -07:00
clk-wm831x.c	clk: make clk_init_data const	2017-11-01 23:25:51 -07:00
clk-xgene.c	clk: clk-xgene: Adjust six checks for null pointers	2017-11-13 17:40:03 -08:00
clk.c	The core framework has a handful of patches this time around, mostly due	2018-02-01 16:56:07 -08:00
clk.h	clk: Move __clk_{get,put}() into private clk.h API	2018-01-04 15:13:29 -08:00
clkdev.c	clk: Prepare to remove asm-generic/clkdev.h	2018-01-02 16:12:00 -08:00
Kconfig	Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into clk-next	2018-01-26 16:43:39 -08:00
Makefile	Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner' into clk-next	2018-01-26 16:43:39 -08:00