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6ebbf2ce43
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
107 lines
2.1 KiB
C
107 lines
2.1 KiB
C
#include <asm/assembler.h>
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#include <asm/unwind.h>
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#if __LINUX_ARM_ARCH__ >= 6
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.macro bitop, name, instr
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strneb r1, [ip] @ assert word-aligned
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mov r2, #1
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and r3, r0, #31 @ Get bit offset
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mov r0, r0, lsr #5
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add r1, r1, r0, lsl #2 @ Get word offset
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#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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.arch_extension mp
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ALT_SMP(W(pldw) [r1])
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ALT_UP(W(nop))
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#endif
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mov r3, r2, lsl r3
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1: ldrex r2, [r1]
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\instr r2, r2, r3
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strex r0, r2, [r1]
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cmp r0, #0
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bne 1b
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bx lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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.macro testop, name, instr, store
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strneb r1, [ip] @ assert word-aligned
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mov r2, #1
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and r3, r0, #31 @ Get bit offset
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mov r0, r0, lsr #5
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add r1, r1, r0, lsl #2 @ Get word offset
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mov r3, r2, lsl r3 @ create mask
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smp_dmb
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#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
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.arch_extension mp
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ALT_SMP(W(pldw) [r1])
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ALT_UP(W(nop))
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#endif
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1: ldrex r2, [r1]
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ands r0, r2, r3 @ save old value of bit
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\instr r2, r2, r3 @ toggle bit
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strex ip, r2, [r1]
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cmp ip, #0
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bne 1b
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smp_dmb
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cmp r0, #0
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movne r0, #1
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2: bx lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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#else
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.macro bitop, name, instr
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strneb r1, [ip] @ assert word-aligned
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and r2, r0, #31
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mov r0, r0, lsr #5
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mov r3, #1
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mov r3, r3, lsl r2
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save_and_disable_irqs ip
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ldr r2, [r1, r0, lsl #2]
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\instr r2, r2, r3
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str r2, [r1, r0, lsl #2]
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restore_irqs ip
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ret lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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/**
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* testop - implement a test_and_xxx_bit operation.
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* @instr: operational instruction
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* @store: store instruction
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*
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* Note: we can trivially conditionalise the store instruction
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* to avoid dirtying the data cache.
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*/
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.macro testop, name, instr, store
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ENTRY( \name )
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UNWIND( .fnstart )
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ands ip, r1, #3
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strneb r1, [ip] @ assert word-aligned
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and r3, r0, #31
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mov r0, r0, lsr #5
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save_and_disable_irqs ip
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ldr r2, [r1, r0, lsl #2]!
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mov r0, #1
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tst r2, r0, lsl r3
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\instr r2, r2, r0, lsl r3
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\store r2, [r1]
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moveq r0, #0
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restore_irqs ip
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ret lr
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UNWIND( .fnend )
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ENDPROC(\name )
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.endm
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#endif
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