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5aa8484080
umem->nmap is used while allocating internal buffer for storing page DMA addresses. This causes out of bounds array access while iterating the umem DMA-mapped SGL with umem page combining as umem->nmap can be less than number of system pages in umem. Use ib_umem_num_pages() instead of umem->nmap to size the page array. Add a new structure (bnxt_qplib_sg_info) to pass sglist, npages and nmap. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
800 lines
23 KiB
C
800 lines
23 KiB
C
/*
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* Broadcom NetXtreme-E RoCE driver.
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*
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
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* Broadcom refers to Broadcom Limited and/or its subsidiaries.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Description: RDMA Controller HW interface
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*/
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#define dev_fmt(fmt) "QPLIB: " fmt
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/prefetch.h>
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#include <linux/delay.h>
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#include "roce_hsi.h"
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#include "qplib_res.h"
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#include "qplib_rcfw.h"
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#include "qplib_sp.h"
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#include "qplib_fp.h"
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static void bnxt_qplib_service_creq(unsigned long data);
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/* Hardware communication channel */
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static int __wait_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
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{
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u16 cbit;
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int rc;
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cbit = cookie % rcfw->cmdq_depth;
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rc = wait_event_timeout(rcfw->waitq,
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!test_bit(cbit, rcfw->cmdq_bitmap),
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msecs_to_jiffies(RCFW_CMD_WAIT_TIME_MS));
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return rc ? 0 : -ETIMEDOUT;
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};
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static int __block_for_resp(struct bnxt_qplib_rcfw *rcfw, u16 cookie)
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{
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u32 count = RCFW_BLOCKED_CMD_WAIT_COUNT;
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u16 cbit;
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cbit = cookie % rcfw->cmdq_depth;
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if (!test_bit(cbit, rcfw->cmdq_bitmap))
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goto done;
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do {
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mdelay(1); /* 1m sec */
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bnxt_qplib_service_creq((unsigned long)rcfw);
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} while (test_bit(cbit, rcfw->cmdq_bitmap) && --count);
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done:
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return count ? 0 : -ETIMEDOUT;
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};
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static int __send_message(struct bnxt_qplib_rcfw *rcfw, struct cmdq_base *req,
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struct creq_base *resp, void *sb, u8 is_block)
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{
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struct bnxt_qplib_cmdqe *cmdqe, **cmdq_ptr;
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struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
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u32 cmdq_depth = rcfw->cmdq_depth;
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struct bnxt_qplib_crsq *crsqe;
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u32 sw_prod, cmdq_prod;
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unsigned long flags;
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u32 size, opcode;
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u16 cookie, cbit;
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u8 *preq;
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opcode = req->opcode;
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if (!test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
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(opcode != CMDQ_BASE_OPCODE_QUERY_FUNC &&
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opcode != CMDQ_BASE_OPCODE_INITIALIZE_FW &&
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opcode != CMDQ_BASE_OPCODE_QUERY_VERSION)) {
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dev_err(&rcfw->pdev->dev,
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"RCFW not initialized, reject opcode 0x%x\n", opcode);
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return -EINVAL;
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}
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if (test_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags) &&
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opcode == CMDQ_BASE_OPCODE_INITIALIZE_FW) {
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dev_err(&rcfw->pdev->dev, "RCFW already initialized!\n");
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return -EINVAL;
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}
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if (test_bit(FIRMWARE_TIMED_OUT, &rcfw->flags))
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return -ETIMEDOUT;
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/* Cmdq are in 16-byte units, each request can consume 1 or more
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* cmdqe
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*/
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spin_lock_irqsave(&cmdq->lock, flags);
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if (req->cmd_size >= HWQ_FREE_SLOTS(cmdq)) {
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dev_err(&rcfw->pdev->dev, "RCFW: CMDQ is full!\n");
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spin_unlock_irqrestore(&cmdq->lock, flags);
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return -EAGAIN;
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}
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cookie = rcfw->seq_num & RCFW_MAX_COOKIE_VALUE;
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cbit = cookie % rcfw->cmdq_depth;
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if (is_block)
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cookie |= RCFW_CMD_IS_BLOCKING;
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set_bit(cbit, rcfw->cmdq_bitmap);
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req->cookie = cpu_to_le16(cookie);
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crsqe = &rcfw->crsqe_tbl[cbit];
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if (crsqe->resp) {
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spin_unlock_irqrestore(&cmdq->lock, flags);
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return -EBUSY;
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}
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memset(resp, 0, sizeof(*resp));
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crsqe->resp = (struct creq_qp_event *)resp;
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crsqe->resp->cookie = req->cookie;
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crsqe->req_size = req->cmd_size;
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if (req->resp_size && sb) {
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struct bnxt_qplib_rcfw_sbuf *sbuf = sb;
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req->resp_addr = cpu_to_le64(sbuf->dma_addr);
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req->resp_size = (sbuf->size + BNXT_QPLIB_CMDQE_UNITS - 1) /
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BNXT_QPLIB_CMDQE_UNITS;
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}
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cmdq_ptr = (struct bnxt_qplib_cmdqe **)cmdq->pbl_ptr;
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preq = (u8 *)req;
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size = req->cmd_size * BNXT_QPLIB_CMDQE_UNITS;
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do {
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/* Locate the next cmdq slot */
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sw_prod = HWQ_CMP(cmdq->prod, cmdq);
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cmdqe = &cmdq_ptr[get_cmdq_pg(sw_prod, cmdq_depth)]
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[get_cmdq_idx(sw_prod, cmdq_depth)];
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if (!cmdqe) {
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dev_err(&rcfw->pdev->dev,
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"RCFW request failed with no cmdqe!\n");
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goto done;
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}
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/* Copy a segment of the req cmd to the cmdq */
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memset(cmdqe, 0, sizeof(*cmdqe));
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memcpy(cmdqe, preq, min_t(u32, size, sizeof(*cmdqe)));
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preq += min_t(u32, size, sizeof(*cmdqe));
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size -= min_t(u32, size, sizeof(*cmdqe));
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cmdq->prod++;
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rcfw->seq_num++;
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} while (size > 0);
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rcfw->seq_num++;
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cmdq_prod = cmdq->prod;
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if (test_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags)) {
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/* The very first doorbell write
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* is required to set this flag
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* which prompts the FW to reset
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* its internal pointers
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*/
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cmdq_prod |= BIT(FIRMWARE_FIRST_FLAG);
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clear_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
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}
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/* ring CMDQ DB */
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wmb();
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writel(cmdq_prod, rcfw->cmdq_bar_reg_iomem +
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rcfw->cmdq_bar_reg_prod_off);
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writel(RCFW_CMDQ_TRIG_VAL, rcfw->cmdq_bar_reg_iomem +
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rcfw->cmdq_bar_reg_trig_off);
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done:
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spin_unlock_irqrestore(&cmdq->lock, flags);
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/* Return the CREQ response pointer */
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return 0;
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}
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int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
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struct cmdq_base *req,
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struct creq_base *resp,
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void *sb, u8 is_block)
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{
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struct creq_qp_event *evnt = (struct creq_qp_event *)resp;
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u16 cookie;
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u8 opcode, retry_cnt = 0xFF;
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int rc = 0;
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do {
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opcode = req->opcode;
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rc = __send_message(rcfw, req, resp, sb, is_block);
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cookie = le16_to_cpu(req->cookie) & RCFW_MAX_COOKIE_VALUE;
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if (!rc)
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break;
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if (!retry_cnt || (rc != -EAGAIN && rc != -EBUSY)) {
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/* send failed */
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dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x send failed\n",
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cookie, opcode);
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return rc;
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}
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is_block ? mdelay(1) : usleep_range(500, 1000);
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} while (retry_cnt--);
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if (is_block)
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rc = __block_for_resp(rcfw, cookie);
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else
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rc = __wait_for_resp(rcfw, cookie);
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if (rc) {
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/* timed out */
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dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x timedout (%d)msec\n",
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cookie, opcode, RCFW_CMD_WAIT_TIME_MS);
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set_bit(FIRMWARE_TIMED_OUT, &rcfw->flags);
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return rc;
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}
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if (evnt->status) {
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/* failed with status */
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dev_err(&rcfw->pdev->dev, "cmdq[%#x]=%#x status %#x\n",
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cookie, opcode, evnt->status);
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rc = -EFAULT;
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}
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return rc;
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}
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/* Completions */
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static int bnxt_qplib_process_func_event(struct bnxt_qplib_rcfw *rcfw,
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struct creq_func_event *func_event)
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{
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switch (func_event->event) {
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case CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_CQ_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_TQM_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_CFCS_ERROR:
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/* SRQ ctx error, call srq_handler??
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* But there's no SRQ handle!
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*/
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break;
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case CREQ_FUNC_EVENT_EVENT_CFCC_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_CFCM_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_TIM_ERROR:
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break;
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case CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST:
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break;
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case CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED:
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int bnxt_qplib_process_qp_event(struct bnxt_qplib_rcfw *rcfw,
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struct creq_qp_event *qp_event)
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{
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struct bnxt_qplib_hwq *cmdq = &rcfw->cmdq;
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struct creq_qp_error_notification *err_event;
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struct bnxt_qplib_crsq *crsqe;
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unsigned long flags;
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struct bnxt_qplib_qp *qp;
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u16 cbit, blocked = 0;
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u16 cookie;
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__le16 mcookie;
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u32 qp_id;
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switch (qp_event->event) {
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case CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION:
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err_event = (struct creq_qp_error_notification *)qp_event;
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qp_id = le32_to_cpu(err_event->xid);
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qp = rcfw->qp_tbl[qp_id].qp_handle;
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dev_dbg(&rcfw->pdev->dev,
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"Received QP error notification\n");
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dev_dbg(&rcfw->pdev->dev,
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"qpid 0x%x, req_err=0x%x, resp_err=0x%x\n",
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qp_id, err_event->req_err_state_reason,
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err_event->res_err_state_reason);
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if (!qp)
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break;
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bnxt_qplib_mark_qp_error(qp);
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rcfw->aeq_handler(rcfw, qp_event, qp);
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break;
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default:
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/*
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* Command Response
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* cmdq->lock needs to be acquired to synchronie
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* the command send and completion reaping. This function
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* is always called with creq->lock held. Using
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* the nested variant of spin_lock.
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*
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*/
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spin_lock_irqsave_nested(&cmdq->lock, flags,
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SINGLE_DEPTH_NESTING);
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cookie = le16_to_cpu(qp_event->cookie);
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mcookie = qp_event->cookie;
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blocked = cookie & RCFW_CMD_IS_BLOCKING;
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cookie &= RCFW_MAX_COOKIE_VALUE;
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cbit = cookie % rcfw->cmdq_depth;
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crsqe = &rcfw->crsqe_tbl[cbit];
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if (crsqe->resp &&
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crsqe->resp->cookie == mcookie) {
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memcpy(crsqe->resp, qp_event, sizeof(*qp_event));
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crsqe->resp = NULL;
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} else {
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if (crsqe->resp && crsqe->resp->cookie)
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dev_err(&rcfw->pdev->dev,
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"CMD %s cookie sent=%#x, recd=%#x\n",
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crsqe->resp ? "mismatch" : "collision",
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crsqe->resp ? crsqe->resp->cookie : 0,
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mcookie);
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}
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if (!test_and_clear_bit(cbit, rcfw->cmdq_bitmap))
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dev_warn(&rcfw->pdev->dev,
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"CMD bit %d was not requested\n", cbit);
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cmdq->cons += crsqe->req_size;
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crsqe->req_size = 0;
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if (!blocked)
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wake_up(&rcfw->waitq);
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spin_unlock_irqrestore(&cmdq->lock, flags);
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}
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return 0;
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}
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/* SP - CREQ Completion handlers */
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static void bnxt_qplib_service_creq(unsigned long data)
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{
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struct bnxt_qplib_rcfw *rcfw = (struct bnxt_qplib_rcfw *)data;
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bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
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struct bnxt_qplib_hwq *creq = &rcfw->creq;
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u32 type, budget = CREQ_ENTRY_POLL_BUDGET;
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struct creq_base *creqe, **creq_ptr;
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u32 sw_cons, raw_cons;
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unsigned long flags;
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/* Service the CREQ until budget is over */
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spin_lock_irqsave(&creq->lock, flags);
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raw_cons = creq->cons;
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while (budget > 0) {
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sw_cons = HWQ_CMP(raw_cons, creq);
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creq_ptr = (struct creq_base **)creq->pbl_ptr;
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creqe = &creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)];
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if (!CREQ_CMP_VALID(creqe, raw_cons, creq->max_elements))
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break;
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/* The valid test of the entry must be done first before
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* reading any further.
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*/
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dma_rmb();
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type = creqe->type & CREQ_BASE_TYPE_MASK;
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switch (type) {
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case CREQ_BASE_TYPE_QP_EVENT:
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bnxt_qplib_process_qp_event
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(rcfw, (struct creq_qp_event *)creqe);
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rcfw->creq_qp_event_processed++;
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break;
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case CREQ_BASE_TYPE_FUNC_EVENT:
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if (!bnxt_qplib_process_func_event
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(rcfw, (struct creq_func_event *)creqe))
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rcfw->creq_func_event_processed++;
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else
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dev_warn(&rcfw->pdev->dev,
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"aeqe:%#x Not handled\n", type);
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break;
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default:
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if (type != ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT)
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dev_warn(&rcfw->pdev->dev,
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"creqe with event 0x%x not handled\n",
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type);
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break;
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}
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raw_cons++;
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budget--;
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}
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if (creq->cons != raw_cons) {
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creq->cons = raw_cons;
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bnxt_qplib_ring_creq_db_rearm(rcfw->creq_bar_reg_iomem,
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raw_cons, creq->max_elements,
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rcfw->creq_ring_id, gen_p5);
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}
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spin_unlock_irqrestore(&creq->lock, flags);
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}
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static irqreturn_t bnxt_qplib_creq_irq(int irq, void *dev_instance)
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{
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struct bnxt_qplib_rcfw *rcfw = dev_instance;
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struct bnxt_qplib_hwq *creq = &rcfw->creq;
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struct creq_base **creq_ptr;
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u32 sw_cons;
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/* Prefetch the CREQ element */
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sw_cons = HWQ_CMP(creq->cons, creq);
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creq_ptr = (struct creq_base **)rcfw->creq.pbl_ptr;
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prefetch(&creq_ptr[get_creq_pg(sw_cons)][get_creq_idx(sw_cons)]);
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tasklet_schedule(&rcfw->worker);
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return IRQ_HANDLED;
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}
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/* RCFW */
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int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw)
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{
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struct cmdq_deinitialize_fw req;
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struct creq_deinitialize_fw_resp resp;
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u16 cmd_flags = 0;
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int rc;
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|
|
RCFW_CMD_PREP(req, DEINITIALIZE_FW, cmd_flags);
|
|
rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
|
|
NULL, 0);
|
|
if (rc)
|
|
return rc;
|
|
|
|
clear_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
|
|
return 0;
|
|
}
|
|
|
|
static int __get_pbl_pg_idx(struct bnxt_qplib_pbl *pbl)
|
|
{
|
|
return (pbl->pg_size == ROCE_PG_SIZE_4K ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K :
|
|
pbl->pg_size == ROCE_PG_SIZE_8K ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K :
|
|
pbl->pg_size == ROCE_PG_SIZE_64K ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K :
|
|
pbl->pg_size == ROCE_PG_SIZE_2M ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M :
|
|
pbl->pg_size == ROCE_PG_SIZE_8M ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M :
|
|
pbl->pg_size == ROCE_PG_SIZE_1G ?
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G :
|
|
CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K);
|
|
}
|
|
|
|
int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
|
|
struct bnxt_qplib_ctx *ctx, int is_virtfn)
|
|
{
|
|
struct cmdq_initialize_fw req;
|
|
struct creq_initialize_fw_resp resp;
|
|
u16 cmd_flags = 0, level;
|
|
int rc;
|
|
|
|
RCFW_CMD_PREP(req, INITIALIZE_FW, cmd_flags);
|
|
/* Supply (log-base-2-of-host-page-size - base-page-shift)
|
|
* to bono to adjust the doorbell page sizes.
|
|
*/
|
|
req.log2_dbr_pg_size = cpu_to_le16(PAGE_SHIFT -
|
|
RCFW_DBR_BASE_PAGE_SHIFT);
|
|
/*
|
|
* Gen P5 devices doesn't require this allocation
|
|
* as the L2 driver does the same for RoCE also.
|
|
* Also, VFs need not setup the HW context area, PF
|
|
* shall setup this area for VF. Skipping the
|
|
* HW programming
|
|
*/
|
|
if (is_virtfn || bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))
|
|
goto skip_ctx_setup;
|
|
|
|
level = ctx->qpc_tbl.level;
|
|
req.qpc_pg_size_qpc_lvl = (level << CMDQ_INITIALIZE_FW_QPC_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->qpc_tbl.pbl[level]);
|
|
level = ctx->mrw_tbl.level;
|
|
req.mrw_pg_size_mrw_lvl = (level << CMDQ_INITIALIZE_FW_MRW_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->mrw_tbl.pbl[level]);
|
|
level = ctx->srqc_tbl.level;
|
|
req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
|
|
level = ctx->cq_tbl.level;
|
|
req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
|
|
level = ctx->srqc_tbl.level;
|
|
req.srq_pg_size_srq_lvl = (level << CMDQ_INITIALIZE_FW_SRQ_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->srqc_tbl.pbl[level]);
|
|
level = ctx->cq_tbl.level;
|
|
req.cq_pg_size_cq_lvl = (level << CMDQ_INITIALIZE_FW_CQ_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->cq_tbl.pbl[level]);
|
|
level = ctx->tim_tbl.level;
|
|
req.tim_pg_size_tim_lvl = (level << CMDQ_INITIALIZE_FW_TIM_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->tim_tbl.pbl[level]);
|
|
level = ctx->tqm_pde_level;
|
|
req.tqm_pg_size_tqm_lvl = (level << CMDQ_INITIALIZE_FW_TQM_LVL_SFT) |
|
|
__get_pbl_pg_idx(&ctx->tqm_pde.pbl[level]);
|
|
|
|
req.qpc_page_dir =
|
|
cpu_to_le64(ctx->qpc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
req.mrw_page_dir =
|
|
cpu_to_le64(ctx->mrw_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
req.srq_page_dir =
|
|
cpu_to_le64(ctx->srqc_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
req.cq_page_dir =
|
|
cpu_to_le64(ctx->cq_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
req.tim_page_dir =
|
|
cpu_to_le64(ctx->tim_tbl.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
req.tqm_page_dir =
|
|
cpu_to_le64(ctx->tqm_pde.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
|
|
req.number_of_qp = cpu_to_le32(ctx->qpc_tbl.max_elements);
|
|
req.number_of_mrw = cpu_to_le32(ctx->mrw_tbl.max_elements);
|
|
req.number_of_srq = cpu_to_le32(ctx->srqc_tbl.max_elements);
|
|
req.number_of_cq = cpu_to_le32(ctx->cq_tbl.max_elements);
|
|
|
|
req.max_qp_per_vf = cpu_to_le32(ctx->vf_res.max_qp_per_vf);
|
|
req.max_mrw_per_vf = cpu_to_le32(ctx->vf_res.max_mrw_per_vf);
|
|
req.max_srq_per_vf = cpu_to_le32(ctx->vf_res.max_srq_per_vf);
|
|
req.max_cq_per_vf = cpu_to_le32(ctx->vf_res.max_cq_per_vf);
|
|
req.max_gid_per_vf = cpu_to_le32(ctx->vf_res.max_gid_per_vf);
|
|
|
|
skip_ctx_setup:
|
|
req.stat_ctx_id = cpu_to_le32(ctx->stats.fw_id);
|
|
rc = bnxt_qplib_rcfw_send_message(rcfw, (void *)&req, (void *)&resp,
|
|
NULL, 0);
|
|
if (rc)
|
|
return rc;
|
|
set_bit(FIRMWARE_INITIALIZED_FLAG, &rcfw->flags);
|
|
return 0;
|
|
}
|
|
|
|
void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
|
|
{
|
|
kfree(rcfw->qp_tbl);
|
|
kfree(rcfw->crsqe_tbl);
|
|
bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->cmdq);
|
|
bnxt_qplib_free_hwq(rcfw->pdev, &rcfw->creq);
|
|
rcfw->pdev = NULL;
|
|
}
|
|
|
|
int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
|
|
struct bnxt_qplib_rcfw *rcfw,
|
|
struct bnxt_qplib_ctx *ctx,
|
|
int qp_tbl_sz)
|
|
{
|
|
u8 hwq_type;
|
|
|
|
rcfw->pdev = pdev;
|
|
rcfw->creq.max_elements = BNXT_QPLIB_CREQE_MAX_CNT;
|
|
hwq_type = bnxt_qplib_get_hwq_type(rcfw->res);
|
|
if (bnxt_qplib_alloc_init_hwq(rcfw->pdev, &rcfw->creq, NULL,
|
|
&rcfw->creq.max_elements,
|
|
BNXT_QPLIB_CREQE_UNITS,
|
|
0, PAGE_SIZE, hwq_type)) {
|
|
dev_err(&rcfw->pdev->dev,
|
|
"HW channel CREQ allocation failed\n");
|
|
goto fail;
|
|
}
|
|
if (ctx->hwrm_intf_ver < HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK)
|
|
rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_256;
|
|
else
|
|
rcfw->cmdq_depth = BNXT_QPLIB_CMDQE_MAX_CNT_8192;
|
|
|
|
rcfw->cmdq.max_elements = rcfw->cmdq_depth;
|
|
if (bnxt_qplib_alloc_init_hwq
|
|
(rcfw->pdev, &rcfw->cmdq, NULL,
|
|
&rcfw->cmdq.max_elements,
|
|
BNXT_QPLIB_CMDQE_UNITS, 0,
|
|
bnxt_qplib_cmdqe_page_size(rcfw->cmdq_depth),
|
|
HWQ_TYPE_CTX)) {
|
|
dev_err(&rcfw->pdev->dev,
|
|
"HW channel CMDQ allocation failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
rcfw->crsqe_tbl = kcalloc(rcfw->cmdq.max_elements,
|
|
sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
|
|
if (!rcfw->crsqe_tbl)
|
|
goto fail;
|
|
|
|
rcfw->qp_tbl_size = qp_tbl_sz;
|
|
rcfw->qp_tbl = kcalloc(qp_tbl_sz, sizeof(struct bnxt_qplib_qp_node),
|
|
GFP_KERNEL);
|
|
if (!rcfw->qp_tbl)
|
|
goto fail;
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
bnxt_qplib_free_rcfw_channel(rcfw);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
void bnxt_qplib_rcfw_stop_irq(struct bnxt_qplib_rcfw *rcfw, bool kill)
|
|
{
|
|
bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
|
|
|
|
tasklet_disable(&rcfw->worker);
|
|
/* Mask h/w interrupts */
|
|
bnxt_qplib_ring_creq_db(rcfw->creq_bar_reg_iomem, rcfw->creq.cons,
|
|
rcfw->creq.max_elements, rcfw->creq_ring_id,
|
|
gen_p5);
|
|
/* Sync with last running IRQ-handler */
|
|
synchronize_irq(rcfw->vector);
|
|
if (kill)
|
|
tasklet_kill(&rcfw->worker);
|
|
|
|
if (rcfw->requested) {
|
|
free_irq(rcfw->vector, rcfw);
|
|
rcfw->requested = false;
|
|
}
|
|
}
|
|
|
|
void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw)
|
|
{
|
|
unsigned long indx;
|
|
|
|
bnxt_qplib_rcfw_stop_irq(rcfw, true);
|
|
|
|
iounmap(rcfw->cmdq_bar_reg_iomem);
|
|
iounmap(rcfw->creq_bar_reg_iomem);
|
|
|
|
indx = find_first_bit(rcfw->cmdq_bitmap, rcfw->bmap_size);
|
|
if (indx != rcfw->bmap_size)
|
|
dev_err(&rcfw->pdev->dev,
|
|
"disabling RCFW with pending cmd-bit %lx\n", indx);
|
|
kfree(rcfw->cmdq_bitmap);
|
|
rcfw->bmap_size = 0;
|
|
|
|
rcfw->cmdq_bar_reg_iomem = NULL;
|
|
rcfw->creq_bar_reg_iomem = NULL;
|
|
rcfw->aeq_handler = NULL;
|
|
rcfw->vector = 0;
|
|
}
|
|
|
|
int bnxt_qplib_rcfw_start_irq(struct bnxt_qplib_rcfw *rcfw, int msix_vector,
|
|
bool need_init)
|
|
{
|
|
bool gen_p5 = bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx);
|
|
int rc;
|
|
|
|
if (rcfw->requested)
|
|
return -EFAULT;
|
|
|
|
rcfw->vector = msix_vector;
|
|
if (need_init)
|
|
tasklet_init(&rcfw->worker,
|
|
bnxt_qplib_service_creq, (unsigned long)rcfw);
|
|
else
|
|
tasklet_enable(&rcfw->worker);
|
|
rc = request_irq(rcfw->vector, bnxt_qplib_creq_irq, 0,
|
|
"bnxt_qplib_creq", rcfw);
|
|
if (rc)
|
|
return rc;
|
|
rcfw->requested = true;
|
|
bnxt_qplib_ring_creq_db_rearm(rcfw->creq_bar_reg_iomem,
|
|
rcfw->creq.cons, rcfw->creq.max_elements,
|
|
rcfw->creq_ring_id, gen_p5);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
|
|
struct bnxt_qplib_rcfw *rcfw,
|
|
int msix_vector,
|
|
int cp_bar_reg_off, int virt_fn,
|
|
int (*aeq_handler)(struct bnxt_qplib_rcfw *,
|
|
void *, void *))
|
|
{
|
|
resource_size_t res_base;
|
|
struct cmdq_init init;
|
|
u16 bmap_size;
|
|
int rc;
|
|
|
|
/* General */
|
|
rcfw->seq_num = 0;
|
|
set_bit(FIRMWARE_FIRST_FLAG, &rcfw->flags);
|
|
bmap_size = BITS_TO_LONGS(rcfw->cmdq_depth) * sizeof(unsigned long);
|
|
rcfw->cmdq_bitmap = kzalloc(bmap_size, GFP_KERNEL);
|
|
if (!rcfw->cmdq_bitmap)
|
|
return -ENOMEM;
|
|
rcfw->bmap_size = bmap_size;
|
|
|
|
/* CMDQ */
|
|
rcfw->cmdq_bar_reg = RCFW_COMM_PCI_BAR_REGION;
|
|
res_base = pci_resource_start(pdev, rcfw->cmdq_bar_reg);
|
|
if (!res_base)
|
|
return -ENOMEM;
|
|
|
|
rcfw->cmdq_bar_reg_iomem = ioremap_nocache(res_base +
|
|
RCFW_COMM_BASE_OFFSET,
|
|
RCFW_COMM_SIZE);
|
|
if (!rcfw->cmdq_bar_reg_iomem) {
|
|
dev_err(&rcfw->pdev->dev, "CMDQ BAR region %d mapping failed\n",
|
|
rcfw->cmdq_bar_reg);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
rcfw->cmdq_bar_reg_prod_off = virt_fn ? RCFW_VF_COMM_PROD_OFFSET :
|
|
RCFW_PF_COMM_PROD_OFFSET;
|
|
|
|
rcfw->cmdq_bar_reg_trig_off = RCFW_COMM_TRIG_OFFSET;
|
|
|
|
/* CREQ */
|
|
rcfw->creq_bar_reg = RCFW_COMM_CONS_PCI_BAR_REGION;
|
|
res_base = pci_resource_start(pdev, rcfw->creq_bar_reg);
|
|
if (!res_base)
|
|
dev_err(&rcfw->pdev->dev,
|
|
"CREQ BAR region %d resc start is 0!\n",
|
|
rcfw->creq_bar_reg);
|
|
/* Unconditionally map 8 bytes to support 57500 series */
|
|
rcfw->creq_bar_reg_iomem = ioremap_nocache(res_base + cp_bar_reg_off,
|
|
8);
|
|
if (!rcfw->creq_bar_reg_iomem) {
|
|
dev_err(&rcfw->pdev->dev, "CREQ BAR region %d mapping failed\n",
|
|
rcfw->creq_bar_reg);
|
|
iounmap(rcfw->cmdq_bar_reg_iomem);
|
|
rcfw->cmdq_bar_reg_iomem = NULL;
|
|
return -ENOMEM;
|
|
}
|
|
rcfw->creq_qp_event_processed = 0;
|
|
rcfw->creq_func_event_processed = 0;
|
|
|
|
if (aeq_handler)
|
|
rcfw->aeq_handler = aeq_handler;
|
|
init_waitqueue_head(&rcfw->waitq);
|
|
|
|
rc = bnxt_qplib_rcfw_start_irq(rcfw, msix_vector, true);
|
|
if (rc) {
|
|
dev_err(&rcfw->pdev->dev,
|
|
"Failed to request IRQ for CREQ rc = 0x%x\n", rc);
|
|
bnxt_qplib_disable_rcfw_channel(rcfw);
|
|
return rc;
|
|
}
|
|
|
|
init.cmdq_pbl = cpu_to_le64(rcfw->cmdq.pbl[PBL_LVL_0].pg_map_arr[0]);
|
|
init.cmdq_size_cmdq_lvl = cpu_to_le16(
|
|
((rcfw->cmdq_depth << CMDQ_INIT_CMDQ_SIZE_SFT) &
|
|
CMDQ_INIT_CMDQ_SIZE_MASK) |
|
|
((rcfw->cmdq.level << CMDQ_INIT_CMDQ_LVL_SFT) &
|
|
CMDQ_INIT_CMDQ_LVL_MASK));
|
|
init.creq_ring_id = cpu_to_le16(rcfw->creq_ring_id);
|
|
|
|
/* Write to the Bono mailbox register */
|
|
__iowrite32_copy(rcfw->cmdq_bar_reg_iomem, &init, sizeof(init) / 4);
|
|
return 0;
|
|
}
|
|
|
|
struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
|
|
struct bnxt_qplib_rcfw *rcfw,
|
|
u32 size)
|
|
{
|
|
struct bnxt_qplib_rcfw_sbuf *sbuf;
|
|
|
|
sbuf = kzalloc(sizeof(*sbuf), GFP_ATOMIC);
|
|
if (!sbuf)
|
|
return NULL;
|
|
|
|
sbuf->size = size;
|
|
sbuf->sb = dma_alloc_coherent(&rcfw->pdev->dev, sbuf->size,
|
|
&sbuf->dma_addr, GFP_ATOMIC);
|
|
if (!sbuf->sb)
|
|
goto bail;
|
|
|
|
return sbuf;
|
|
bail:
|
|
kfree(sbuf);
|
|
return NULL;
|
|
}
|
|
|
|
void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
|
|
struct bnxt_qplib_rcfw_sbuf *sbuf)
|
|
{
|
|
if (sbuf->sb)
|
|
dma_free_coherent(&rcfw->pdev->dev, sbuf->size,
|
|
sbuf->sb, sbuf->dma_addr);
|
|
kfree(sbuf);
|
|
}
|