mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 15:04:27 +08:00
eab3540562
Various driver updates for platforms:
- Nvidia: Fuse support for Tegra194, continued memory controller pieces
for Tegra30
- NXP/FSL: Refactorings of QuickEngine drivers to support ARM/ARM64/PPC
- NXP/FSL: i.MX8MP SoC driver pieces
- TI Keystone: ring accelerator driver
- Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.
- Xilinx ZynqMP: feature checking interface for firmware. Mailbox
communication for power management
- Overall support patch set for cpuidle on more complex hierarchies
(PSCI-based)
+ Misc cleanups, refactorings of Marvell, TI, other platforms.
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl4+lTYPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3nQcQAJm91+6hZbmMjlBySGS7ISjYvOcrI/hMgiOl
uhhEP0Dcylvf9A9x3wcIbLwixe+2pvie9DQh2u5F80ShYimidtFi/2xCfuTb9fKu
sxxKjrXWyVKhkpW0z+tedY08ftVhkwwcyD4m2C7uVl6AwTP7c367vFeU7XjF2APn
drfgmgbjm8U3XbSyAqv+k6z6tyqaCnFM7vbPupSKHgHJ3mfByxOa+XyBN2RdgBbs
0KrVfbXGv80zFIFrMPwaWG7G52bu7K68nVdgy44MpKdRZ6QTjhnR+kerFxHsYgV4
bM55Fya52nTCSTGdKaQakDtKwbAUdCDTSkxgOHGcQoyFi0R/VaEUJtcysnvLbI6c
+n/yFIzGyEdXcvIzfv2SoDYhogw19I6RR/M9K5Ni29eazkDVYx2z3rI+2QYeqCiF
u7cq52gW6JLP0SI/9kuUrRFiR8v19Ixap7qokAxgqQwYB3NzT8a7WsYPkzdpDZGQ
ETSDFMyBWT6UvBe/HWkQluBabbet53rG8BF0OHFrQuMK0u/ieKgSGuTB9XN2djEW
PHMOMz2vhi+8XTfpkskhF2tTxlA/k4R6QwCdIMpIkMRVnVQCh1XdPr3Fi2NrgB+S
kIXHD4vV6zLYh04zHyKewSPHAXWgraFpg2qKnvL5+KWMTnW6QH+RNjOt9xKDNXOd
+iDXpOad
=ONtb
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms:
- Nvidia: Fuse support for Tegra194, continued memory controller
pieces for Tegra30
- NXP/FSL: Refactorings of QuickEngine drivers to support
ARM/ARM64/PPC
- NXP/FSL: i.MX8MP SoC driver pieces
- TI Keystone: ring accelerator driver
- Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.
- Xilinx ZynqMP: feature checking interface for firmware. Mailbox
communication for power management
- Overall support patch set for cpuidle on more complex hierarchies
(PSCI-based)
and misc cleanups, refactorings of Marvell, TI, other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits)
drivers: soc: xilinx: Use mailbox IPI callback
dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox
drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists
MAINTAINERS: Add brcmstb PCIe controller entry
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
soc/tegra: regulators: Do nothing if voltage is unchanged
memory: tegra: Correct reset value of xusb_hostr
soc/tegra: fuse: Add APB DMA dependency for Tegra20
bus: tegra-aconnect: Remove PM_CLK dependency
dt-bindings: mediatek: add MT6765 power dt-bindings
soc: mediatek: cmdq: delete not used define
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
...
123 lines
3.0 KiB
C
123 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* Author: Michael Johnston <michael.johnston@freescale.com>
|
|
*
|
|
* Description:
|
|
* TWR-P102x Board Setup
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/fsl/guts.h>
|
|
#include <linux/pci.h>
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <asm/pci-bridge.h>
|
|
#include <asm/udbg.h>
|
|
#include <asm/mpic.h>
|
|
#include <soc/fsl/qe/qe.h>
|
|
|
|
#include <sysdev/fsl_soc.h>
|
|
#include <sysdev/fsl_pci.h>
|
|
#include "smp.h"
|
|
|
|
#include "mpc85xx.h"
|
|
|
|
static void __init twr_p1025_pic_init(void)
|
|
{
|
|
struct mpic *mpic;
|
|
|
|
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
|
|
MPIC_SINGLE_DEST_CPU,
|
|
0, 256, " OpenPIC ");
|
|
|
|
BUG_ON(mpic == NULL);
|
|
mpic_init(mpic);
|
|
}
|
|
|
|
/* ************************************************************************
|
|
*
|
|
* Setup the architecture
|
|
*
|
|
*/
|
|
static void __init twr_p1025_setup_arch(void)
|
|
{
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("twr_p1025_setup_arch()", 0);
|
|
|
|
mpc85xx_smp_init();
|
|
|
|
fsl_pci_assign_primary();
|
|
|
|
#ifdef CONFIG_QUICC_ENGINE
|
|
mpc85xx_qe_par_io_init();
|
|
|
|
#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
|
|
if (machine_is(twr_p1025)) {
|
|
struct ccsr_guts __iomem *guts;
|
|
struct device_node *np;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
|
|
if (np) {
|
|
guts = of_iomap(np, 0);
|
|
if (!guts)
|
|
pr_err("twr_p1025: could not map global utilities register\n");
|
|
else {
|
|
/* P1025 has pins muxed for QE and other functions. To
|
|
* enable QE UEC mode, we need to set bit QE0 for UCC1
|
|
* in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
|
|
* and QE12 for QE MII management signals in PMUXCR
|
|
* register.
|
|
* Set QE mux bits in PMUXCR */
|
|
setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
|
|
MPC85xx_PMUXCR_QE(3) |
|
|
MPC85xx_PMUXCR_QE(9) |
|
|
MPC85xx_PMUXCR_QE(12));
|
|
iounmap(guts);
|
|
|
|
#if IS_ENABLED(CONFIG_SERIAL_QE)
|
|
/* On P1025TWR board, the UCC7 acted as UART port.
|
|
* However, The UCC7's CTS pin is low level in default,
|
|
* it will impact the transmission in full duplex
|
|
* communication. So disable the Flow control pin PA18.
|
|
* The UCC7 UART just can use RXD and TXD pins.
|
|
*/
|
|
par_io_config_pin(0, 18, 0, 0, 0, 0);
|
|
#endif
|
|
/* Drive PB29 to CPLD low - CPLD will then change
|
|
* muxing from LBC to QE */
|
|
par_io_config_pin(1, 29, 1, 0, 0, 0);
|
|
par_io_data_set(1, 29, 0);
|
|
}
|
|
of_node_put(np);
|
|
}
|
|
}
|
|
#endif
|
|
#endif /* CONFIG_QUICC_ENGINE */
|
|
|
|
pr_info("TWR-P1025 board from Freescale Semiconductor\n");
|
|
}
|
|
|
|
machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
|
|
|
|
static int __init twr_p1025_probe(void)
|
|
{
|
|
return of_machine_is_compatible("fsl,TWR-P1025");
|
|
}
|
|
|
|
define_machine(twr_p1025) {
|
|
.name = "TWR-P1025",
|
|
.probe = twr_p1025_probe,
|
|
.setup_arch = twr_p1025_setup_arch,
|
|
.init_IRQ = twr_p1025_pic_init,
|
|
#ifdef CONFIG_PCI
|
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
|
#endif
|
|
.get_irq = mpic_get_irq,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.progress = udbg_progress,
|
|
};
|