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Add defines for stream IDs used for Host1x context isolation on Tegra234. The same stream IDs are used for both NISO0 and NISO1 SMMUs since Host1x's stream ID protection tables don't make a distinction between the two. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
144 lines
4.6 KiB
C
144 lines
4.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
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/* special clients */
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#define TEGRA234_SID_INVALID 0x00
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#define TEGRA234_SID_PASSTHROUGH 0x7f
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/* NISO0 stream IDs */
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#define TEGRA234_SID_APE 0x02
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#define TEGRA234_SID_HDA 0x03
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#define TEGRA234_SID_GPCDMA 0x04
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#define TEGRA234_SID_MGBE 0x06
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#define TEGRA234_SID_PCIE0 0x12
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#define TEGRA234_SID_PCIE4 0x13
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#define TEGRA234_SID_PCIE5 0x14
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#define TEGRA234_SID_PCIE6 0x15
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#define TEGRA234_SID_PCIE9 0x1f
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#define TEGRA234_SID_MGBE_VF1 0x49
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#define TEGRA234_SID_MGBE_VF2 0x4a
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#define TEGRA234_SID_MGBE_VF3 0x4b
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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#define TEGRA234_SID_PCIE1 0x05
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#define TEGRA234_SID_PCIE2 0x06
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#define TEGRA234_SID_PCIE3 0x07
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#define TEGRA234_SID_PCIE7 0x08
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#define TEGRA234_SID_PCIE8 0x09
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#define TEGRA234_SID_PCIE10 0x0b
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#define TEGRA234_SID_BPMP 0x10
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#define TEGRA234_SID_HOST1X 0x27
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#define TEGRA234_SID_VIC 0x34
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/* Shared stream IDs */
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#define TEGRA234_SID_HOST1X_CTX0 0x35
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#define TEGRA234_SID_HOST1X_CTX1 0x36
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#define TEGRA234_SID_HOST1X_CTX2 0x37
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#define TEGRA234_SID_HOST1X_CTX3 0x38
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#define TEGRA234_SID_HOST1X_CTX4 0x39
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#define TEGRA234_SID_HOST1X_CTX5 0x3a
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#define TEGRA234_SID_HOST1X_CTX6 0x3b
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#define TEGRA234_SID_HOST1X_CTX7 0x3c
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/*
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* memory client IDs
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*/
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/* High-definition audio (HDA) read clients */
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#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
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#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
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/* PCIE6 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
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/* PCIE6 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
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/* PCIE7 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
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/* PCIE7 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
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/* PCIE8 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
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/* High-definition audio (HDA) write clients */
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#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
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/* PCIE8 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
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/* PCIE9 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
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/* PCIE6r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
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/* PCIE9 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
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/* PCIE10 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
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/* PCIE10 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
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/* PCIE10r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
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/* PCIE7r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
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/* MGBE0 read client */
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#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
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/* MGBEB read client */
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#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
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/* MGBEC read client */
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#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
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/* MGBED read client */
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#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
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/* MGBE0 write client */
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#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
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/* MGBEB write client */
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#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
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/* MGBEC write client */
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#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
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/* sdmmcd memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
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/* MGBED write client */
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#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
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/* sdmmcd memory write client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
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#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
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#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
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/* BPMP read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
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/* BPMPDMA read client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
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/* APEDMA read client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
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/* APEDMA write client */
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#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
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/* PCIE0 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
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/* PCIE0 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
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/* PCIE1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
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/* PCIE1 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
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/* PCIE2 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
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/* PCIE2 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
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/* PCIE3 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
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/* PCIE3 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
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/* PCIE4 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
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/* PCIE4 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
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/* PCIE5 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
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/* PCIE5 write clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
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/* PCIE5r1 read clients */
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#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
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#endif
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