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linux/tools/testing/cxl
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Li Ming 2c402bd2e8 cxl/test: Skip cxl_setup_parent_dport() for emulated dports 
The cxl_test unit test environment on qemu always hits below call trace
with KASAN enabled:

 BUG: KASAN: slab-out-of-bounds in cxl_setup_parent_dport+0x480/0x530 [cxl_core]
 Read of size 1 at addr ff110000676014f8 by task (udev-worker)/676[   24.424403] CPU: 2 PID: 676 Comm: (udev-worker) Tainted: G           O     N 6.10.0-qemucxl #1
 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240214-2.el9 02/14/2024
 Call Trace:
  <TASK>
  dump_stack_lvl+0xea/0x150
  print_report+0xce/0x610
  ? kasan_complete_mode_report_info+0x40/0x200
  kasan_report+0xcc/0x110
  __asan_report_load1_noabort+0x18/0x20
  cxl_setup_parent_dport+0x480/0x530 [cxl_core]
  cxl_mem_probe+0x49b/0xaa0 [cxl_mem]

cxl_test module models a CXL topology for testing, it creates some
emulated dports with platform devices in the CXL topology, so the
dport_dev of an emulated dport points to a platform device rather than a
pci device or a pci host bridge in the case. Currently,
cxl_setup_parent_dport() is used to set up RAS and AER capability on the
dport connected to the CXL memory device, but cxl_test does not support
RAS or AER functionality yet, so the fix is implementing a
__wrap_cxl_setup_parent_dport() to filter out all emulated dports,
guarantees only real dports can be handled by cxl_setup_parent_dport().

Fixes: f05fd10d13 ("cxl/pci: Add RCH downstream port AER register discovery")
Reported-by: Pengfei Xu <pengfei.xu@intel.com>
Closes: https://lore.kernel.org/linux-cxl/ZrHTBp2O+HtUe6kt@xpf.sh.intel.com/T/#t
Signed-off-by: Li Ming <ming4.li@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Tested-by: Ira Weiny <ira.weiny@intel.com>
Tested-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240809082750.3015641-3-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2024-08-09 15:14:12 -07:00
..
test cxl/test: Skip cxl_setup_parent_dport() for emulated dports 2024-08-09 15:14:12 -07:00
config_check.c tools/testing/cxl: Require CONFIG_DEBUG_FS 2023-04-23 12:08:39 -07:00
cxl_acpi_test.c tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00
cxl_core_exports.c cxl: Add cxl_num_decoders_committed() usage to cxl_test 2023-12-04 16:46:14 -08:00
cxl_core_test.c tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00
cxl_mem_test.c tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00
cxl_pmem_test.c tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00
cxl_port_test.c tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00
Kbuild cxl/test: Skip cxl_setup_parent_dport() for emulated dports 2024-08-09 15:14:12 -07:00
mock_acpi.c cxl/core: Generalize dport enumeration in the core 2022-02-08 22:57:30 -08:00
watermark.h tools/testing/cxl: Prevent cxl_test from confusing production modules 2023-01-05 15:01:45 -08:00