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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
355 lines
6.9 KiB
C
355 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
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*
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* Geode GX2 header information
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*/
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#ifndef _GXFB_H_
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#define _GXFB_H_
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#include <linux/io.h>
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#define GP_REG_COUNT (0x50 / 4)
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#define DC_REG_COUNT (0x90 / 4)
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#define VP_REG_COUNT (0x138 / 8)
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#define FP_REG_COUNT (0x68 / 8)
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#define DC_PAL_COUNT 0x104
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struct gxfb_par {
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int enable_crt;
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void __iomem *dc_regs;
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void __iomem *vid_regs;
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void __iomem *gp_regs;
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#ifdef CONFIG_PM
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int powered_down;
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/* register state, for power management functionality */
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struct {
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uint64_t padsel;
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uint64_t dotpll;
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} msr;
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uint32_t gp[GP_REG_COUNT];
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uint32_t dc[DC_REG_COUNT];
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uint64_t vp[VP_REG_COUNT];
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uint64_t fp[FP_REG_COUNT];
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uint32_t pal[DC_PAL_COUNT];
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#endif
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};
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unsigned int gx_frame_buffer_size(void);
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int gx_line_delta(int xres, int bpp);
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void gx_set_mode(struct fb_info *info);
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void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
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unsigned red, unsigned green, unsigned blue);
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void gx_set_dclk_frequency(struct fb_info *info);
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void gx_configure_display(struct fb_info *info);
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int gx_blank_display(struct fb_info *info, int blank_mode);
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#ifdef CONFIG_PM
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int gx_powerdown(struct fb_info *info);
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int gx_powerup(struct fb_info *info);
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#endif
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/* Graphics Processor registers (table 6-23 from the data book) */
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enum gp_registers {
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GP_DST_OFFSET = 0,
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GP_SRC_OFFSET,
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GP_STRIDE,
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GP_WID_HEIGHT,
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GP_SRC_COLOR_FG,
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GP_SRC_COLOR_BG,
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GP_PAT_COLOR_0,
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GP_PAT_COLOR_1,
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GP_PAT_COLOR_2,
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GP_PAT_COLOR_3,
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GP_PAT_COLOR_4,
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GP_PAT_COLOR_5,
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GP_PAT_DATA_0,
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GP_PAT_DATA_1,
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GP_RASTER_MODE,
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GP_VECTOR_MODE,
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GP_BLT_MODE,
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GP_BLT_STATUS,
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GP_HST_SRC,
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GP_BASE_OFFSET, /* 0x4c */
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};
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#define GP_BLT_STATUS_BLT_PENDING (1 << 2)
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#define GP_BLT_STATUS_BLT_BUSY (1 << 0)
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/* Display Controller registers (table 6-38 from the data book) */
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enum dc_registers {
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DC_UNLOCK = 0,
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DC_GENERAL_CFG,
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DC_DISPLAY_CFG,
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DC_RSVD_0,
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DC_FB_ST_OFFSET,
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DC_CB_ST_OFFSET,
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DC_CURS_ST_OFFSET,
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DC_ICON_ST_OFFSET,
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DC_VID_Y_ST_OFFSET,
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DC_VID_U_ST_OFFSET,
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DC_VID_V_ST_OFFSET,
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DC_RSVD_1,
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DC_LINE_SIZE,
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DC_GFX_PITCH,
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DC_VID_YUV_PITCH,
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DC_RSVD_2,
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DC_H_ACTIVE_TIMING,
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DC_H_BLANK_TIMING,
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DC_H_SYNC_TIMING,
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DC_RSVD_3,
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DC_V_ACTIVE_TIMING,
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DC_V_BLANK_TIMING,
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DC_V_SYNC_TIMING,
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DC_RSVD_4,
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DC_CURSOR_X,
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DC_CURSOR_Y,
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DC_ICON_X,
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DC_LINE_CNT,
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DC_PAL_ADDRESS,
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DC_PAL_DATA,
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DC_DFIFO_DIAG,
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DC_CFIFO_DIAG,
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DC_VID_DS_DELTA,
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DC_GLIU0_MEM_OFFSET,
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DC_RSVD_5,
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DC_DV_ACC, /* 0x8c */
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};
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#define DC_UNLOCK_LOCK 0x00000000
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#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
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#define DC_GENERAL_CFG_YUVM (1 << 20)
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#define DC_GENERAL_CFG_VDSE (1 << 19)
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#define DC_GENERAL_CFG_DFHPEL_SHIFT 12
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#define DC_GENERAL_CFG_DFHPSL_SHIFT 8
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#define DC_GENERAL_CFG_DECE (1 << 6)
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#define DC_GENERAL_CFG_CMPE (1 << 5)
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#define DC_GENERAL_CFG_VIDE (1 << 3)
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#define DC_GENERAL_CFG_ICNE (1 << 2)
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#define DC_GENERAL_CFG_CURE (1 << 1)
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#define DC_GENERAL_CFG_DFLE (1 << 0)
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#define DC_DISPLAY_CFG_A20M (1 << 31)
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#define DC_DISPLAY_CFG_A18M (1 << 30)
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#define DC_DISPLAY_CFG_PALB (1 << 25)
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#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
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#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
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#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
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#define DC_DISPLAY_CFG_VDEN (1 << 4)
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#define DC_DISPLAY_CFG_GDEN (1 << 3)
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#define DC_DISPLAY_CFG_TGEN (1 << 0)
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/*
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* Video Processor registers (table 6-54).
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* There is space for 64 bit values, but we never use more than the
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* lower 32 bits. The actual register save/restore code only bothers
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* to restore those 32 bits.
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*/
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enum vp_registers {
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VP_VCFG = 0,
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VP_DCFG,
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VP_VX,
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VP_VY,
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VP_VS,
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VP_VCK,
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VP_VCM,
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VP_GAR,
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VP_GDR,
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VP_RSVD_0,
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VP_MISC,
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VP_CCS,
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VP_RSVD_1,
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VP_RSVD_2,
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VP_RSVD_3,
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VP_VDC,
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VP_VCO,
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VP_CRC,
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VP_CRC32,
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VP_VDE,
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VP_CCK,
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VP_CCM,
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VP_CC1,
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VP_CC2,
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VP_A1X,
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VP_A1Y,
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VP_A1C,
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VP_A1T,
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VP_A2X,
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VP_A2Y,
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VP_A2C,
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VP_A2T,
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VP_A3X,
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VP_A3Y,
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VP_A3C,
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VP_A3T,
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VP_VRR,
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VP_AWT,
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VP_VTM, /* 0x130 */
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};
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#define VP_VCFG_VID_EN (1 << 0)
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#define VP_DCFG_DAC_VREF (1 << 26)
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#define VP_DCFG_GV_GAM (1 << 21)
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#define VP_DCFG_VG_CK (1 << 20)
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#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
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#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
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#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
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#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
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#define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */
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#define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */
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#define VP_DCFG_DAC_BL_EN (1 << 3)
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#define VP_DCFG_VSYNC_EN (1 << 2)
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#define VP_DCFG_HSYNC_EN (1 << 1)
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#define VP_DCFG_CRT_EN (1 << 0)
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#define VP_MISC_GAM_EN (1 << 0)
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#define VP_MISC_DACPWRDN (1 << 10)
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#define VP_MISC_APWRDN (1 << 11)
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/*
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* Flat Panel registers (table 6-55).
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* Also 64 bit registers; see above note about 32-bit handling.
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*/
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/* we're actually in the VP register space, starting at address 0x400 */
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#define VP_FP_START 0x400
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enum fp_registers {
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FP_PT1 = 0,
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FP_PT2,
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FP_PM,
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FP_DFC,
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FP_BLFSR,
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FP_RLFSR,
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FP_FMI,
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FP_FMD,
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FP_RSVD_0,
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FP_DCA,
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FP_DMD,
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FP_CRC,
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FP_FBB, /* 0x460 */
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};
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#define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */
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#define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */
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#define FP_PT2_HSP (1 << 22)
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#define FP_PT2_VSP (1 << 23)
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#define FP_PM_P (1 << 24) /* panel power on */
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#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
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#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
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#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
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#define FP_PM_PANEL_ON (1 << 0) /* r/o */
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#define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6))
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/* register access functions */
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static inline uint32_t read_gp(struct gxfb_par *par, int reg)
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{
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return readl(par->gp_regs + 4*reg);
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}
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static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->gp_regs + 4*reg);
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}
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static inline uint32_t read_dc(struct gxfb_par *par, int reg)
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{
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return readl(par->dc_regs + 4*reg);
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}
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static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->dc_regs + 4*reg);
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}
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static inline uint32_t read_vp(struct gxfb_par *par, int reg)
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{
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return readl(par->vid_regs + 8*reg);
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}
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static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vid_regs + 8*reg);
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}
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static inline uint32_t read_fp(struct gxfb_par *par, int reg)
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{
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return readl(par->vid_regs + 8*reg + VP_FP_START);
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}
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static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
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{
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writel(val, par->vid_regs + 8*reg + VP_FP_START);
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}
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/* MSRs are defined in linux/cs5535.h; their bitfields are here */
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#define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3)
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#define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2)
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#define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1)
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#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
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#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
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#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
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#define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */
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#define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */
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#define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3)
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#endif
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