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The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and can't be used for wait state insertion for NAND I/O read/write. So disable read/write wait monitoring as per Reference Manual's suggestion [1]. [1] AM437x TRM: SPRUHL7D: 9.1.3.3.12.2 NAND Device-Ready Pin Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> |
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