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When the 5-level page table CPU flag is set in the host, but the guest has CR4.LA57=0 (including the case of a 32-bit guest), the top level of the shadow NPT page tables will be fixed, consisting of one pointer to a lower-level table and 511 non-present entries. Extend the existing code that creates the fixed PML4 or PDP table, to provide a fixed PML5 table if needed. This is not needed on EPT because the number of layers in the tables is specified in the EPTP instead of depending on the host CR4. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Wei Huang <wei.huang2@amd.com> Message-Id: <20210818165549.3771014-3-wei.huang2@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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mmu_audit.c | ||
mmu_internal.h | ||
mmu.c | ||
mmutrace.h | ||
page_track.c | ||
paging_tmpl.h | ||
paging.h | ||
spte.c | ||
spte.h | ||
tdp_iter.c | ||
tdp_iter.h | ||
tdp_mmu.c | ||
tdp_mmu.h |