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d61feec0f6
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20190727150738.54764-29-yuehaibing@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
520 lines
13 KiB
C
520 lines
13 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <sound/pcm_params.h>
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#define SPDIFIN_CTRL0 0x00
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#define SPDIFIN_CTRL0_EN BIT(31)
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#define SPDIFIN_CTRL0_RST_OUT BIT(29)
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#define SPDIFIN_CTRL0_RST_IN BIT(28)
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#define SPDIFIN_CTRL0_WIDTH_SEL BIT(24)
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#define SPDIFIN_CTRL0_STATUS_CH_SHIFT 11
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#define SPDIFIN_CTRL0_STATUS_SEL GENMASK(10, 8)
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#define SPDIFIN_CTRL0_SRC_SEL GENMASK(5, 4)
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#define SPDIFIN_CTRL0_CHK_VALID BIT(3)
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#define SPDIFIN_CTRL1 0x04
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#define SPDIFIN_CTRL1_BASE_TIMER GENMASK(19, 0)
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#define SPDIFIN_CTRL1_IRQ_MASK GENMASK(27, 20)
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#define SPDIFIN_CTRL2 0x08
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#define SPDIFIN_THRES_PER_REG 3
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#define SPDIFIN_THRES_WIDTH 10
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#define SPDIFIN_CTRL3 0x0c
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#define SPDIFIN_CTRL4 0x10
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#define SPDIFIN_TIMER_PER_REG 4
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#define SPDIFIN_TIMER_WIDTH 8
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#define SPDIFIN_CTRL5 0x14
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#define SPDIFIN_CTRL6 0x18
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#define SPDIFIN_STAT0 0x1c
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#define SPDIFIN_STAT0_MODE GENMASK(30, 28)
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#define SPDIFIN_STAT0_MAXW GENMASK(17, 8)
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#define SPDIFIN_STAT0_IRQ GENMASK(7, 0)
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#define SPDIFIN_IRQ_MODE_CHANGED BIT(2)
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#define SPDIFIN_STAT1 0x20
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#define SPDIFIN_STAT2 0x24
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#define SPDIFIN_MUTE_VAL 0x28
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#define SPDIFIN_MODE_NUM 7
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struct axg_spdifin_cfg {
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const unsigned int *mode_rates;
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unsigned int ref_rate;
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};
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struct axg_spdifin {
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const struct axg_spdifin_cfg *conf;
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struct regmap *map;
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struct clk *refclk;
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struct clk *pclk;
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};
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/*
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* TODO:
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* It would have been nice to check the actual rate against the sample rate
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* requested in hw_params(). Unfortunately, I was not able to make the mode
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* detection and IRQ work reliably:
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*
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* 1. IRQs are generated on mode change only, so there is no notification
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* on transition between no signal and mode 0 (32kHz).
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* 2. Mode detection very often has glitches, and may detects the
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* lowest or the highest mode before zeroing in on the actual mode.
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*
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* This makes calling snd_pcm_stop() difficult to get right. Even notifying
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* the kcontrol would be very unreliable at this point.
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* Let's keep things simple until the magic spell that makes this work is
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* found.
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*/
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static unsigned int axg_spdifin_get_rate(struct axg_spdifin *priv)
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{
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unsigned int stat, mode, rate = 0;
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regmap_read(priv->map, SPDIFIN_STAT0, &stat);
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mode = FIELD_GET(SPDIFIN_STAT0_MODE, stat);
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/*
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* If max width is zero, we are not capturing anything.
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* Also Sometimes, when the capture is on but there is no data,
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* mode is SPDIFIN_MODE_NUM, but not always ...
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*/
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if (FIELD_GET(SPDIFIN_STAT0_MAXW, stat) &&
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mode < SPDIFIN_MODE_NUM)
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rate = priv->conf->mode_rates[mode];
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return rate;
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}
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static int axg_spdifin_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
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/* Apply both reset */
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regmap_update_bits(priv->map, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_RST_OUT |
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SPDIFIN_CTRL0_RST_IN,
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0);
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/* Clear out reset before in reset */
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regmap_update_bits(priv->map, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_RST_OUT, SPDIFIN_CTRL0_RST_OUT);
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regmap_update_bits(priv->map, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_RST_IN, SPDIFIN_CTRL0_RST_IN);
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return 0;
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}
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static int axg_spdifin_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
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int ret;
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ret = clk_prepare_enable(priv->refclk);
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if (ret) {
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dev_err(dai->dev,
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"failed to enable spdifin reference clock\n");
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return ret;
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}
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regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN,
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SPDIFIN_CTRL0_EN);
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return 0;
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}
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static void axg_spdifin_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
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regmap_update_bits(priv->map, SPDIFIN_CTRL0, SPDIFIN_CTRL0_EN, 0);
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clk_disable_unprepare(priv->refclk);
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}
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static void axg_spdifin_write_mode_param(struct regmap *map, int mode,
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unsigned int val,
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unsigned int num_per_reg,
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unsigned int base_reg,
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unsigned int width)
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{
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uint64_t offset = mode;
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unsigned int reg, shift, rem;
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rem = do_div(offset, num_per_reg);
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reg = offset * regmap_get_reg_stride(map) + base_reg;
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shift = width * (num_per_reg - 1 - rem);
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regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift,
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val << shift);
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}
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static void axg_spdifin_write_timer(struct regmap *map, int mode,
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unsigned int val)
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{
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axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_TIMER_PER_REG,
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SPDIFIN_CTRL4, SPDIFIN_TIMER_WIDTH);
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}
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static void axg_spdifin_write_threshold(struct regmap *map, int mode,
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unsigned int val)
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{
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axg_spdifin_write_mode_param(map, mode, val, SPDIFIN_THRES_PER_REG,
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SPDIFIN_CTRL2, SPDIFIN_THRES_WIDTH);
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}
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static unsigned int axg_spdifin_mode_timer(struct axg_spdifin *priv,
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int mode,
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unsigned int rate)
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{
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/*
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* Number of period of the reference clock during a period of the
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* input signal reference clock
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*/
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return rate / (128 * priv->conf->mode_rates[mode]);
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}
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static int axg_spdifin_sample_mode_config(struct snd_soc_dai *dai,
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struct axg_spdifin *priv)
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{
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unsigned int rate, t_next;
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int ret, i = SPDIFIN_MODE_NUM - 1;
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/* Set spdif input reference clock */
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ret = clk_set_rate(priv->refclk, priv->conf->ref_rate);
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if (ret) {
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dev_err(dai->dev, "reference clock rate set failed\n");
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return ret;
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}
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/*
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* The rate actually set might be slightly different, get
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* the actual rate for the following mode calculation
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*/
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rate = clk_get_rate(priv->refclk);
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/* HW will update mode every 1ms */
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regmap_update_bits(priv->map, SPDIFIN_CTRL1,
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SPDIFIN_CTRL1_BASE_TIMER,
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FIELD_PREP(SPDIFIN_CTRL1_BASE_TIMER, rate / 1000));
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/* Threshold based on the minimum width between two edges */
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regmap_update_bits(priv->map, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_WIDTH_SEL, SPDIFIN_CTRL0_WIDTH_SEL);
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/* Calculate the last timer which has no threshold */
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t_next = axg_spdifin_mode_timer(priv, i, rate);
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axg_spdifin_write_timer(priv->map, i, t_next);
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do {
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unsigned int t;
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i -= 1;
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/* Calculate the timer */
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t = axg_spdifin_mode_timer(priv, i, rate);
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/* Set the timer value */
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axg_spdifin_write_timer(priv->map, i, t);
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/* Set the threshold value */
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axg_spdifin_write_threshold(priv->map, i, t + t_next);
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/* Save the current timer for the next threshold calculation */
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t_next = t;
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} while (i > 0);
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return 0;
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}
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static int axg_spdifin_dai_probe(struct snd_soc_dai *dai)
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{
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struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
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int ret;
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ret = clk_prepare_enable(priv->pclk);
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if (ret) {
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dev_err(dai->dev, "failed to enable pclk\n");
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return ret;
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}
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ret = axg_spdifin_sample_mode_config(dai, priv);
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if (ret) {
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dev_err(dai->dev, "mode configuration failed\n");
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clk_disable_unprepare(priv->pclk);
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return ret;
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}
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return 0;
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}
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static int axg_spdifin_dai_remove(struct snd_soc_dai *dai)
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{
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struct axg_spdifin *priv = snd_soc_dai_get_drvdata(dai);
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clk_disable_unprepare(priv->pclk);
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return 0;
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}
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static const struct snd_soc_dai_ops axg_spdifin_ops = {
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.prepare = axg_spdifin_prepare,
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.startup = axg_spdifin_startup,
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.shutdown = axg_spdifin_shutdown,
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};
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static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
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uinfo->count = 1;
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return 0;
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}
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static int axg_spdifin_get_status_mask(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int i;
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for (i = 0; i < 24; i++)
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ucontrol->value.iec958.status[i] = 0xff;
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return 0;
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}
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static int axg_spdifin_get_status(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
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struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
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int i, j;
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for (i = 0; i < 6; i++) {
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unsigned int val;
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regmap_update_bits(priv->map, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_STATUS_SEL,
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FIELD_PREP(SPDIFIN_CTRL0_STATUS_SEL, i));
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regmap_read(priv->map, SPDIFIN_STAT1, &val);
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for (j = 0; j < 4; j++) {
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unsigned int offset = i * 4 + j;
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ucontrol->value.iec958.status[offset] =
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(val >> (j * 8)) & 0xff;
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}
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}
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return 0;
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}
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#define AXG_SPDIFIN_IEC958_MASK \
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{ \
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.access = SNDRV_CTL_ELEM_ACCESS_READ, \
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.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
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.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), \
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.info = axg_spdifin_iec958_info, \
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.get = axg_spdifin_get_status_mask, \
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}
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#define AXG_SPDIFIN_IEC958_STATUS \
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{ \
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.access = (SNDRV_CTL_ELEM_ACCESS_READ | \
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SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
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.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
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.name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE), \
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.info = axg_spdifin_iec958_info, \
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.get = axg_spdifin_get_status, \
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}
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static const char * const spdifin_chsts_src_texts[] = {
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"A", "B",
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};
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static SOC_ENUM_SINGLE_DECL(axg_spdifin_chsts_src_enum, SPDIFIN_CTRL0,
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SPDIFIN_CTRL0_STATUS_CH_SHIFT,
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spdifin_chsts_src_texts);
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static int axg_spdifin_rate_lock_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
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uinfo->count = 1;
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uinfo->value.integer.min = 0;
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uinfo->value.integer.max = 192000;
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return 0;
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}
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static int axg_spdifin_rate_lock_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *c = snd_kcontrol_chip(kcontrol);
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struct axg_spdifin *priv = snd_soc_component_get_drvdata(c);
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ucontrol->value.integer.value[0] = axg_spdifin_get_rate(priv);
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return 0;
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}
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#define AXG_SPDIFIN_LOCK_RATE(xname) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_PCM, \
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.access = (SNDRV_CTL_ELEM_ACCESS_READ | \
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SNDRV_CTL_ELEM_ACCESS_VOLATILE), \
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.get = axg_spdifin_rate_lock_get, \
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.info = axg_spdifin_rate_lock_info, \
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.name = xname, \
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}
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static const struct snd_kcontrol_new axg_spdifin_controls[] = {
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AXG_SPDIFIN_LOCK_RATE("Capture Rate Lock"),
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SOC_DOUBLE("Capture Switch", SPDIFIN_CTRL0, 7, 6, 1, 1),
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SOC_ENUM(SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Src",
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axg_spdifin_chsts_src_enum),
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AXG_SPDIFIN_IEC958_MASK,
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AXG_SPDIFIN_IEC958_STATUS,
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};
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static const struct snd_soc_component_driver axg_spdifin_component_drv = {
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.controls = axg_spdifin_controls,
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.num_controls = ARRAY_SIZE(axg_spdifin_controls),
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};
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static const struct regmap_config axg_spdifin_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = SPDIFIN_MUTE_VAL,
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};
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static const unsigned int axg_spdifin_mode_rates[SPDIFIN_MODE_NUM] = {
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32000, 44100, 48000, 88200, 96000, 176400, 192000,
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};
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static const struct axg_spdifin_cfg axg_cfg = {
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.mode_rates = axg_spdifin_mode_rates,
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.ref_rate = 333333333,
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};
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static const struct of_device_id axg_spdifin_of_match[] = {
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{
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.compatible = "amlogic,axg-spdifin",
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.data = &axg_cfg,
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}, {}
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};
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MODULE_DEVICE_TABLE(of, axg_spdifin_of_match);
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static struct snd_soc_dai_driver *
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axg_spdifin_get_dai_drv(struct device *dev, struct axg_spdifin *priv)
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{
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struct snd_soc_dai_driver *drv;
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int i;
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drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
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if (!drv)
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return ERR_PTR(-ENOMEM);
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drv->name = "SPDIF Input";
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drv->ops = &axg_spdifin_ops;
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drv->probe = axg_spdifin_dai_probe;
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drv->remove = axg_spdifin_dai_remove;
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drv->capture.stream_name = "Capture";
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drv->capture.channels_min = 1;
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drv->capture.channels_max = 2;
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drv->capture.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
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for (i = 0; i < SPDIFIN_MODE_NUM; i++) {
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unsigned int rb =
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snd_pcm_rate_to_rate_bit(priv->conf->mode_rates[i]);
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if (rb == SNDRV_PCM_RATE_KNOT)
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return ERR_PTR(-EINVAL);
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drv->capture.rates |= rb;
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}
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return drv;
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}
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static int axg_spdifin_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct axg_spdifin *priv;
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struct snd_soc_dai_driver *dai_drv;
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void __iomem *regs;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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platform_set_drvdata(pdev, priv);
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priv->conf = of_device_get_match_data(dev);
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if (!priv->conf) {
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dev_err(dev, "failed to match device\n");
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return -ENODEV;
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}
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
|
|
|
|
priv->map = devm_regmap_init_mmio(dev, regs, &axg_spdifin_regmap_cfg);
|
|
if (IS_ERR(priv->map)) {
|
|
dev_err(dev, "failed to init regmap: %ld\n",
|
|
PTR_ERR(priv->map));
|
|
return PTR_ERR(priv->map);
|
|
}
|
|
|
|
priv->pclk = devm_clk_get(dev, "pclk");
|
|
if (IS_ERR(priv->pclk)) {
|
|
ret = PTR_ERR(priv->pclk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get pclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
priv->refclk = devm_clk_get(dev, "refclk");
|
|
if (IS_ERR(priv->refclk)) {
|
|
ret = PTR_ERR(priv->refclk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to get mclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dai_drv = axg_spdifin_get_dai_drv(dev, priv);
|
|
if (IS_ERR(dai_drv)) {
|
|
dev_err(dev, "failed to get dai driver: %ld\n",
|
|
PTR_ERR(dai_drv));
|
|
return PTR_ERR(dai_drv);
|
|
}
|
|
|
|
return devm_snd_soc_register_component(dev, &axg_spdifin_component_drv,
|
|
dai_drv, 1);
|
|
}
|
|
|
|
static struct platform_driver axg_spdifin_pdrv = {
|
|
.probe = axg_spdifin_probe,
|
|
.driver = {
|
|
.name = "axg-spdifin",
|
|
.of_match_table = axg_spdifin_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(axg_spdifin_pdrv);
|
|
|
|
MODULE_DESCRIPTION("Amlogic AXG SPDIF Input driver");
|
|
MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
|
|
MODULE_LICENSE("GPL v2");
|