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Using a managed buffer will pre-allocate the buffer using snd_pcm_lib_preallocate_pages() and automatically free it when the PCM is destroyed. In addition it will call snd_pcm_lib_malloc_pages() before the driver's hw_params() callback and snd_pcm_lib_free_pages() after the driver's hw_free() callback. This slightly reduces the boilerplate code of the driver. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201218154544.25513-1-lars@metafoo.de Signed-off-by: Mark Brown <broonie@kernel.org>
186 lines
4.8 KiB
C
186 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2020 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/clk.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "aiu.h"
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#include "aiu-fifo.h"
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#define AIU_IEC958_DCU_FF_CTRL_EN BIT(0)
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#define AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE BIT(1)
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#define AIU_IEC958_DCU_FF_CTRL_IRQ_MODE GENMASK(3, 2)
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#define AIU_IEC958_DCU_FF_CTRL_IRQ_OUT_THD BIT(2)
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#define AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ BIT(3)
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#define AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN BIT(4)
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#define AIU_IEC958_DCU_FF_CTRL_BYTE_SEEK BIT(5)
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#define AIU_IEC958_DCU_FF_CTRL_CONTINUE BIT(6)
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#define AIU_MEM_IEC958_CONTROL_ENDIAN GENMASK(5, 3)
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#define AIU_MEM_IEC958_CONTROL_RD_DDR BIT(6)
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#define AIU_MEM_IEC958_CONTROL_MODE_16BIT BIT(7)
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#define AIU_MEM_IEC958_CONTROL_MODE_LINEAR BIT(8)
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#define AIU_MEM_IEC958_BUF_CNTL_INIT BIT(0)
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#define AIU_FIFO_SPDIF_BLOCK 8
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static struct snd_pcm_hardware fifo_spdif_pcm = {
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.info = (SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE),
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.formats = AIU_FORMATS,
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.rate_min = 5512,
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.rate_max = 192000,
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.channels_min = 2,
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.channels_max = 2,
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.period_bytes_min = AIU_FIFO_SPDIF_BLOCK,
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.period_bytes_max = AIU_FIFO_SPDIF_BLOCK * USHRT_MAX,
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.periods_min = 2,
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.periods_max = UINT_MAX,
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/* No real justification for this */
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.buffer_bytes_max = 1 * 1024 * 1024,
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};
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static void fifo_spdif_dcu_enable(struct snd_soc_component *component,
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bool enable)
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{
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snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
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AIU_IEC958_DCU_FF_CTRL_EN,
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enable ? AIU_IEC958_DCU_FF_CTRL_EN : 0);
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}
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static int fifo_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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int ret;
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ret = aiu_fifo_trigger(substream, cmd, dai);
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if (ret)
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return ret;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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fifo_spdif_dcu_enable(component, true);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_STOP:
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fifo_spdif_dcu_enable(component, false);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int fifo_spdif_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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int ret;
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ret = aiu_fifo_prepare(substream, dai);
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if (ret)
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return ret;
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snd_soc_component_update_bits(component,
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AIU_MEM_IEC958_BUF_CNTL,
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AIU_MEM_IEC958_BUF_CNTL_INIT,
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AIU_MEM_IEC958_BUF_CNTL_INIT);
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snd_soc_component_update_bits(component,
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AIU_MEM_IEC958_BUF_CNTL,
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AIU_MEM_IEC958_BUF_CNTL_INIT, 0);
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return 0;
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}
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static int fifo_spdif_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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unsigned int val;
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int ret;
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ret = aiu_fifo_hw_params(substream, params, dai);
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if (ret)
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return ret;
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val = AIU_MEM_IEC958_CONTROL_RD_DDR |
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AIU_MEM_IEC958_CONTROL_MODE_LINEAR;
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switch (params_physical_width(params)) {
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case 16:
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val |= AIU_MEM_IEC958_CONTROL_MODE_16BIT;
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break;
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case 32:
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break;
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default:
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dev_err(dai->dev, "Unsupported physical width %u\n",
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params_physical_width(params));
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AIU_MEM_IEC958_CONTROL,
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AIU_MEM_IEC958_CONTROL_ENDIAN |
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AIU_MEM_IEC958_CONTROL_RD_DDR |
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AIU_MEM_IEC958_CONTROL_MODE_LINEAR |
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AIU_MEM_IEC958_CONTROL_MODE_16BIT,
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val);
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/* Number bytes read by the FIFO between each IRQ */
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snd_soc_component_write(component, AIU_IEC958_BPF,
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params_period_bytes(params));
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/*
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* AUTO_DISABLE and SYNC_HEAD are enabled by default but
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* this should be disabled in PCM (uncompressed) mode
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*/
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snd_soc_component_update_bits(component, AIU_IEC958_DCU_FF_CTRL,
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AIU_IEC958_DCU_FF_CTRL_AUTO_DISABLE |
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AIU_IEC958_DCU_FF_CTRL_IRQ_MODE |
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AIU_IEC958_DCU_FF_CTRL_SYNC_HEAD_EN,
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AIU_IEC958_DCU_FF_CTRL_IRQ_FRAME_READ);
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return 0;
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}
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const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops = {
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.trigger = fifo_spdif_trigger,
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.prepare = fifo_spdif_prepare,
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.hw_params = fifo_spdif_hw_params,
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.startup = aiu_fifo_startup,
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.shutdown = aiu_fifo_shutdown,
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};
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int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aiu *aiu = snd_soc_component_get_drvdata(component);
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struct aiu_fifo *fifo;
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int ret;
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ret = aiu_fifo_dai_probe(dai);
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if (ret)
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return ret;
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fifo = dai->playback_dma_data;
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fifo->pcm = &fifo_spdif_pcm;
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fifo->mem_offset = AIU_MEM_IEC958_START;
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fifo->fifo_block = 1;
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fifo->pclk = aiu->spdif.clks[PCLK].clk;
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fifo->irq = aiu->spdif.irq;
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return 0;
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}
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