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Add support for the i2s and spdif audio outputs (AIU) found in the amlogic Gx SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200213155159.3235792-5-jbrunet@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
210 lines
5.7 KiB
C
210 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2020 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <sound/pcm_params.h>
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#include <sound/pcm_iec958.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "aiu.h"
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#define AIU_958_MISC_NON_PCM BIT(0)
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#define AIU_958_MISC_MODE_16BITS BIT(1)
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#define AIU_958_MISC_16BITS_ALIGN GENMASK(6, 5)
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#define AIU_958_MISC_MODE_32BITS BIT(7)
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#define AIU_958_MISC_U_FROM_STREAM BIT(12)
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#define AIU_958_MISC_FORCE_LR BIT(13)
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#define AIU_958_CTRL_HOLD_EN BIT(0)
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#define AIU_CLK_CTRL_958_DIV_EN BIT(1)
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#define AIU_CLK_CTRL_958_DIV GENMASK(5, 4)
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#define AIU_CLK_CTRL_958_DIV_MORE BIT(12)
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#define AIU_CS_WORD_LEN 4
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#define AIU_958_INTERNAL_DIV 2
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static void
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aiu_encoder_spdif_divider_enable(struct snd_soc_component *component,
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bool enable)
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{
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snd_soc_component_update_bits(component, AIU_CLK_CTRL,
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AIU_CLK_CTRL_958_DIV_EN,
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enable ? AIU_CLK_CTRL_958_DIV_EN : 0);
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}
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static void aiu_encoder_spdif_hold(struct snd_soc_component *component,
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bool enable)
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{
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snd_soc_component_update_bits(component, AIU_958_CTRL,
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AIU_958_CTRL_HOLD_EN,
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enable ? AIU_958_CTRL_HOLD_EN : 0);
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}
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static int
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aiu_encoder_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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aiu_encoder_spdif_hold(component, false);
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return 0;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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aiu_encoder_spdif_hold(component, true);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int aiu_encoder_spdif_setup_cs_word(struct snd_soc_component *component,
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struct snd_pcm_hw_params *params)
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{
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u8 cs[AIU_CS_WORD_LEN];
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unsigned int val;
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int ret;
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ret = snd_pcm_create_iec958_consumer_hw_params(params, cs,
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AIU_CS_WORD_LEN);
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if (ret < 0)
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return ret;
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/* Write the 1st half word */
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val = cs[1] | cs[0] << 8;
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snd_soc_component_write(component, AIU_958_CHSTAT_L0, val);
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snd_soc_component_write(component, AIU_958_CHSTAT_R0, val);
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/* Write the 2nd half word */
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val = cs[3] | cs[2] << 8;
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snd_soc_component_write(component, AIU_958_CHSTAT_L1, val);
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snd_soc_component_write(component, AIU_958_CHSTAT_R1, val);
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return 0;
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}
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static int aiu_encoder_spdif_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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struct aiu *aiu = snd_soc_component_get_drvdata(component);
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unsigned int val = 0, mrate;
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int ret;
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/* Disable the clock while changing the settings */
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aiu_encoder_spdif_divider_enable(component, false);
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switch (params_physical_width(params)) {
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case 16:
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val |= AIU_958_MISC_MODE_16BITS;
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val |= FIELD_PREP(AIU_958_MISC_16BITS_ALIGN, 2);
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break;
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case 32:
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val |= AIU_958_MISC_MODE_32BITS;
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break;
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default:
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dev_err(dai->dev, "Unsupport physical width\n");
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return -EINVAL;
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}
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snd_soc_component_update_bits(component, AIU_958_MISC,
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AIU_958_MISC_NON_PCM |
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AIU_958_MISC_MODE_16BITS |
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AIU_958_MISC_16BITS_ALIGN |
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AIU_958_MISC_MODE_32BITS |
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AIU_958_MISC_FORCE_LR |
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AIU_958_MISC_U_FROM_STREAM,
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val);
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/* Set the stream channel status word */
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ret = aiu_encoder_spdif_setup_cs_word(component, params);
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if (ret) {
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dev_err(dai->dev, "failed to set channel status word\n");
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return ret;
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}
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snd_soc_component_update_bits(component, AIU_CLK_CTRL,
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AIU_CLK_CTRL_958_DIV |
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AIU_CLK_CTRL_958_DIV_MORE,
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FIELD_PREP(AIU_CLK_CTRL_958_DIV,
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__ffs(AIU_958_INTERNAL_DIV)));
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/* 2 * 32bits per subframe * 2 channels = 128 */
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mrate = params_rate(params) * 128 * AIU_958_INTERNAL_DIV;
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ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate);
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if (ret) {
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dev_err(dai->dev, "failed to set mclk rate\n");
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return ret;
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}
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aiu_encoder_spdif_divider_enable(component, true);
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return 0;
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}
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static int aiu_encoder_spdif_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_component *component = dai->component;
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aiu_encoder_spdif_divider_enable(component, false);
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return 0;
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}
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static int aiu_encoder_spdif_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
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int ret;
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/*
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* NOTE: Make sure the spdif block is on its own divider.
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*
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* The spdif can be clocked by the i2s master clock or its own
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* clock. We should (in theory) change the source depending on the
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* origin of the data.
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*
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* However, considering the clocking scheme used on these platforms,
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* the master clocks will pick the same PLL source when they are
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* playing from the same FIFO. The clock should be in sync so, it
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* should not be necessary to reparent the spdif master clock.
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*/
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ret = clk_set_parent(aiu->spdif.clks[MCLK].clk,
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aiu->spdif_mclk);
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if (ret)
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return ret;
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ret = clk_bulk_prepare_enable(aiu->spdif.clk_num, aiu->spdif.clks);
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if (ret)
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dev_err(dai->dev, "failed to enable spdif clocks\n");
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return ret;
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}
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static void aiu_encoder_spdif_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct aiu *aiu = snd_soc_component_get_drvdata(dai->component);
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clk_bulk_disable_unprepare(aiu->spdif.clk_num, aiu->spdif.clks);
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}
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const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops = {
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.trigger = aiu_encoder_spdif_trigger,
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.hw_params = aiu_encoder_spdif_hw_params,
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.hw_free = aiu_encoder_spdif_hw_free,
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.startup = aiu_encoder_spdif_startup,
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.shutdown = aiu_encoder_spdif_shutdown,
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};
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