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9dc9fd9484
This patch adds a bunch of fixes
1. Reduce sg table size to 64 (SG_MX) instead of default SG_ALL
2. clear task lists on phy down events
3. release all tasks on port deformation
4. release current task for device gone notification
5. Add sata abort handing
6. Add 10ms delay to each port reset (currently done serially and with
interrupts disabled)
[jejb: whitespace fixes and clean ups plus added description
added dummy 94xx_clear_srs_irq function just to prevent the
mismatch in the mvs_dispatch structure killing 94xx cards]
Signed-off-by: Srinivas <satyasrinivasp@hcl.in>
Cc: Andy Yan <ayan@marvell.com>
Cc: qswang@marvell.com
Cc: jfeng@marvell.com
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
683 lines
16 KiB
C
683 lines
16 KiB
C
/*
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* Marvell 88SE94xx hardware specific
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*
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* Copyright 2007 Red Hat, Inc.
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* Copyright 2008 Marvell. <kewei@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include "mv_sas.h"
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#include "mv_94xx.h"
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#include "mv_chips.h"
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static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
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{
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u32 reg;
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struct mvs_phy *phy = &mvi->phy[i];
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u32 phy_status;
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mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
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reg = mvs_read_port_vsr_data(mvi, i);
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phy_status = ((reg & 0x3f0000) >> 16) & 0xff;
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phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
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switch (phy_status) {
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case 0x10:
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phy->phy_type |= PORT_TYPE_SAS;
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break;
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case 0x1d:
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default:
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phy->phy_type |= PORT_TYPE_SATA;
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break;
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}
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}
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static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(MVS_PCS);
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tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
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mw32(MVS_PCS, tmp);
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}
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static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
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{
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u32 tmp;
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tmp = mvs_read_port_irq_stat(mvi, phy_id);
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tmp &= ~PHYEV_RDY_CH;
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mvs_write_port_irq_stat(mvi, phy_id, tmp);
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if (hard) {
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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tmp |= PHY_RST_HARD;
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mvs_write_phy_ctl(mvi, phy_id, tmp);
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do {
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tmp = mvs_read_phy_ctl(mvi, phy_id);
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} while (tmp & PHY_RST_HARD);
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} else {
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_STAT);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp |= PHY_RST;
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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}
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}
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static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
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{
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u32 tmp;
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
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}
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static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
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{
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mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4);
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mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
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mvs_write_port_vsr_addr(mvi, phy_id, 0x104);
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mvs_write_port_vsr_data(mvi, phy_id, 0x00018080);
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
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mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff);
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}
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static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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int i;
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u32 tmp, cctl;
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mvs_show_pcie_usage(mvi);
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if (mvi->flags & MVF_FLAG_SOC) {
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tmp = mr32(MVS_PHY_CTL);
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tmp &= ~PCTL_PWR_OFF;
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tmp |= PCTL_PHY_DSBL;
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mw32(MVS_PHY_CTL, tmp);
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}
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/* Init Chip */
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/* make sure RST is set; HBA_RST /should/ have done that for us */
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cctl = mr32(MVS_CTL) & 0xFFFF;
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if (cctl & CCTL_RST)
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cctl &= ~CCTL_RST;
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else
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mw32_f(MVS_CTL, cctl | CCTL_RST);
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if (mvi->flags & MVF_FLAG_SOC) {
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tmp = mr32(MVS_PHY_CTL);
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tmp &= ~PCTL_PWR_OFF;
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tmp |= PCTL_COM_ON;
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tmp &= ~PCTL_PHY_DSBL;
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tmp |= PCTL_LINK_RST;
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mw32(MVS_PHY_CTL, tmp);
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msleep(100);
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tmp &= ~PCTL_LINK_RST;
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mw32(MVS_PHY_CTL, tmp);
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msleep(100);
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}
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/* reset control */
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mw32(MVS_PCS, 0); /* MVS_PCS */
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mw32(MVS_STP_REG_SET_0, 0);
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mw32(MVS_STP_REG_SET_1, 0);
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/* init phys */
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mvs_phy_hacks(mvi);
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/* disable Multiplexing, enable phy implemented */
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mw32(MVS_PORTS_IMP, 0xFF);
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mw32(MVS_PA_VSR_ADDR, 0x00000104);
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mw32(MVS_PA_VSR_PORT, 0x00018080);
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mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8);
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mw32(MVS_PA_VSR_PORT, 0x0084ffff);
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/* set LED blink when IO*/
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mw32(MVS_PA_VSR_ADDR, 0x00000030);
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tmp = mr32(MVS_PA_VSR_PORT);
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tmp &= 0xFFFF00FF;
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tmp |= 0x00003300;
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mw32(MVS_PA_VSR_PORT, tmp);
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mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
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mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
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mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
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mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
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mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
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mw32(MVS_TX_LO, mvi->tx_dma);
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mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
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mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
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mw32(MVS_RX_LO, mvi->rx_dma);
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mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
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for (i = 0; i < mvi->chip->n_phy; i++) {
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mvs_94xx_phy_disable(mvi, i);
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/* set phy local SAS address */
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mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
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(mvi->phy[i].dev_sas_addr));
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mvs_94xx_enable_xmt(mvi, i);
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mvs_94xx_phy_enable(mvi, i);
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mvs_94xx_phy_reset(mvi, i, 1);
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msleep(500);
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mvs_94xx_detect_porttype(mvi, i);
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}
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if (mvi->flags & MVF_FLAG_SOC) {
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/* set select registers */
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writel(0x0E008000, regs + 0x000);
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writel(0x59000008, regs + 0x004);
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writel(0x20, regs + 0x008);
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writel(0x20, regs + 0x00c);
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writel(0x20, regs + 0x010);
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writel(0x20, regs + 0x014);
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writel(0x20, regs + 0x018);
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writel(0x20, regs + 0x01c);
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}
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for (i = 0; i < mvi->chip->n_phy; i++) {
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/* clear phy int status */
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tmp = mvs_read_port_irq_stat(mvi, i);
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tmp &= ~PHYEV_SIG_FIS;
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mvs_write_port_irq_stat(mvi, i, tmp);
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/* set phy int mask */
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tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
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PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
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mvs_write_port_irq_mask(mvi, i, tmp);
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msleep(100);
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mvs_update_phyinfo(mvi, i, 1);
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}
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/* FIXME: update wide port bitmaps */
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/* little endian for open address and command table, etc. */
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/*
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* it seems that ( from the spec ) turning on big-endian won't
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* do us any good on big-endian machines, need further confirmation
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*/
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cctl = mr32(MVS_CTL);
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cctl |= CCTL_ENDIAN_CMD;
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cctl |= CCTL_ENDIAN_DATA;
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cctl &= ~CCTL_ENDIAN_OPEN;
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cctl |= CCTL_ENDIAN_RSP;
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mw32_f(MVS_CTL, cctl);
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/* reset CMD queue */
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tmp = mr32(MVS_PCS);
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tmp |= PCS_CMD_RST;
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mw32(MVS_PCS, tmp);
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/* interrupt coalescing may cause missing HW interrput in some case,
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* and the max count is 0x1ff, while our max slot is 0x200,
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* it will make count 0.
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*/
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tmp = 0;
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mw32(MVS_INT_COAL, tmp);
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tmp = 0x100;
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mw32(MVS_INT_COAL_TMOUT, tmp);
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/* ladies and gentlemen, start your engines */
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mw32(MVS_TX_CFG, 0);
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mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
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mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
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/* enable CMD/CMPL_Q/RESP mode */
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mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
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PCS_CMD_EN | PCS_CMD_STOP_ERR);
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/* enable completion queue interrupt */
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tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
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CINT_DMA_PCIE);
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tmp |= CINT_PHY_MASK;
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mw32(MVS_INT_MASK, tmp);
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/* Enable SRS interrupt */
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mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
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return 0;
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}
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static int mvs_94xx_ioremap(struct mvs_info *mvi)
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{
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if (!mvs_ioremap(mvi, 2, -1)) {
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mvi->regs_ex = mvi->regs + 0x10200;
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mvi->regs += 0x20000;
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if (mvi->id == 1)
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mvi->regs += 0x4000;
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return 0;
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}
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return -1;
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}
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static void mvs_94xx_iounmap(struct mvs_info *mvi)
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{
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if (mvi->regs) {
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mvi->regs -= 0x20000;
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if (mvi->id == 1)
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mvi->regs -= 0x4000;
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mvs_iounmap(mvi->regs);
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}
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}
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static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs_ex;
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u32 tmp;
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tmp = mr32(MVS_GBL_CTL);
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tmp |= (IRQ_SAS_A | IRQ_SAS_B);
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mw32(MVS_GBL_INT_STAT, tmp);
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writel(tmp, regs + 0x0C);
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writel(tmp, regs + 0x10);
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writel(tmp, regs + 0x14);
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writel(tmp, regs + 0x18);
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mw32(MVS_GBL_CTL, tmp);
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}
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static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs_ex;
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u32 tmp;
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tmp = mr32(MVS_GBL_CTL);
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tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
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mw32(MVS_GBL_INT_STAT, tmp);
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writel(tmp, regs + 0x0C);
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writel(tmp, regs + 0x10);
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writel(tmp, regs + 0x14);
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writel(tmp, regs + 0x18);
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mw32(MVS_GBL_CTL, tmp);
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}
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static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
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{
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void __iomem *regs = mvi->regs_ex;
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u32 stat = 0;
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if (!(mvi->flags & MVF_FLAG_SOC)) {
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stat = mr32(MVS_GBL_INT_STAT);
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if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
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return 0;
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}
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return stat;
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}
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static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
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{
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void __iomem *regs = mvi->regs;
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if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
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((stat & IRQ_SAS_B) && mvi->id == 1)) {
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mw32_f(MVS_INT_STAT, CINT_DONE);
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#ifndef MVS_USE_TASKLET
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spin_lock(&mvi->lock);
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#endif
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mvs_int_full(mvi);
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#ifndef MVS_USE_TASKLET
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spin_unlock(&mvi->lock);
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#endif
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}
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return IRQ_HANDLED;
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}
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static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
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{
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u32 tmp;
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mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));
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do {
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tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));
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} while (tmp & 1 << (slot_idx % 32));
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}
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static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
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u32 tfs)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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if (type == PORT_TYPE_SATA) {
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tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
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mw32(MVS_INT_STAT_SRS_0, tmp);
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}
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mw32(MVS_INT_STAT, CINT_CI_STOP);
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tmp = mr32(MVS_PCS) | 0xFF00;
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mw32(MVS_PCS, tmp);
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}
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static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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u8 reg_set = *tfs;
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if (*tfs == MVS_ID_NOT_MAPPED)
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return;
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mvi->sata_reg_set &= ~bit(reg_set);
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if (reg_set < 32) {
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w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
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tmp = mr32(MVS_INT_STAT_SRS_0) & (u32)mvi->sata_reg_set;
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if (tmp)
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mw32(MVS_INT_STAT_SRS_0, tmp);
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} else {
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w_reg_set_enable(reg_set, mvi->sata_reg_set);
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tmp = mr32(MVS_INT_STAT_SRS_1) & mvi->sata_reg_set;
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if (tmp)
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mw32(MVS_INT_STAT_SRS_1, tmp);
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}
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*tfs = MVS_ID_NOT_MAPPED;
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return;
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}
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static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
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{
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int i;
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void __iomem *regs = mvi->regs;
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if (*tfs != MVS_ID_NOT_MAPPED)
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return 0;
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i = mv_ffc64(mvi->sata_reg_set);
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if (i > 32) {
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mvi->sata_reg_set |= bit(i);
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w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
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*tfs = i;
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return 0;
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} else if (i >= 0) {
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mvi->sata_reg_set |= bit(i);
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w_reg_set_enable(i, (u32)mvi->sata_reg_set);
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*tfs = i;
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return 0;
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}
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return MVS_ID_NOT_MAPPED;
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}
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static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
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{
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int i;
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struct scatterlist *sg;
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struct mvs_prd *buf_prd = prd;
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for_each_sg(scatter, sg, nr, i) {
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buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
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buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
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buf_prd++;
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}
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}
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static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
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{
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u32 phy_st;
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phy_st = mvs_read_phy_ctl(mvi, i);
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if (phy_st & PHY_READY_MASK) /* phy ready */
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return 1;
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return 0;
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}
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static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
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struct sas_identify_frame *id)
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{
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|
int i;
|
|
u32 id_frame[7];
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
mvs_write_port_cfg_addr(mvi, port_id,
|
|
CONFIG_ID_FRAME0 + i * 4);
|
|
id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
|
|
}
|
|
memcpy(id, id_frame, 28);
|
|
}
|
|
|
|
static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
|
|
struct sas_identify_frame *id)
|
|
{
|
|
int i;
|
|
u32 id_frame[7];
|
|
|
|
/* mvs_hexdump(28, (u8 *)id_frame, 0); */
|
|
for (i = 0; i < 7; i++) {
|
|
mvs_write_port_cfg_addr(mvi, port_id,
|
|
CONFIG_ATT_ID_FRAME0 + i * 4);
|
|
id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
|
|
mv_dprintk("94xx phy %d atta frame %d %x.\n",
|
|
port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
|
|
}
|
|
/* mvs_hexdump(28, (u8 *)id_frame, 0); */
|
|
memcpy(id, id_frame, 28);
|
|
}
|
|
|
|
static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id)
|
|
{
|
|
u32 att_dev_info = 0;
|
|
|
|
att_dev_info |= id->dev_type;
|
|
if (id->stp_iport)
|
|
att_dev_info |= PORT_DEV_STP_INIT;
|
|
if (id->smp_iport)
|
|
att_dev_info |= PORT_DEV_SMP_INIT;
|
|
if (id->ssp_iport)
|
|
att_dev_info |= PORT_DEV_SSP_INIT;
|
|
if (id->stp_tport)
|
|
att_dev_info |= PORT_DEV_STP_TRGT;
|
|
if (id->smp_tport)
|
|
att_dev_info |= PORT_DEV_SMP_TRGT;
|
|
if (id->ssp_tport)
|
|
att_dev_info |= PORT_DEV_SSP_TRGT;
|
|
|
|
att_dev_info |= (u32)id->phy_id<<24;
|
|
return att_dev_info;
|
|
}
|
|
|
|
static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id)
|
|
{
|
|
return mvs_94xx_make_dev_info(id);
|
|
}
|
|
|
|
static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
|
|
struct sas_identify_frame *id)
|
|
{
|
|
struct mvs_phy *phy = &mvi->phy[i];
|
|
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
|
mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status);
|
|
sas_phy->linkrate =
|
|
(phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
|
|
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
|
|
sas_phy->linkrate += 0x8;
|
|
mv_dprintk("get link rate is %d\n", sas_phy->linkrate);
|
|
phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
|
|
phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
|
|
mvs_94xx_get_dev_identify_frame(mvi, i, id);
|
|
phy->dev_info = mvs_94xx_make_dev_info(id);
|
|
|
|
if (phy->phy_type & PORT_TYPE_SAS) {
|
|
mvs_94xx_get_att_identify_frame(mvi, i, id);
|
|
phy->att_dev_info = mvs_94xx_make_att_info(id);
|
|
phy->att_dev_sas_addr = *(u64 *)id->sas_addr;
|
|
} else {
|
|
phy->att_dev_info = PORT_DEV_STP_TRGT | 1;
|
|
}
|
|
|
|
}
|
|
|
|
void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
|
|
struct sas_phy_linkrates *rates)
|
|
{
|
|
/* TODO */
|
|
}
|
|
|
|
static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
|
|
{
|
|
u32 tmp;
|
|
void __iomem *regs = mvi->regs;
|
|
tmp = mr32(MVS_STP_REG_SET_0);
|
|
mw32(MVS_STP_REG_SET_0, 0);
|
|
mw32(MVS_STP_REG_SET_0, tmp);
|
|
tmp = mr32(MVS_STP_REG_SET_1);
|
|
mw32(MVS_STP_REG_SET_1, 0);
|
|
mw32(MVS_STP_REG_SET_1, tmp);
|
|
}
|
|
|
|
|
|
u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
|
|
{
|
|
void __iomem *regs = mvi->regs_ex - 0x10200;
|
|
return mr32(SPI_RD_DATA_REG_94XX);
|
|
}
|
|
|
|
void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
|
|
{
|
|
void __iomem *regs = mvi->regs_ex - 0x10200;
|
|
mw32(SPI_RD_DATA_REG_94XX, data);
|
|
}
|
|
|
|
|
|
int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
|
|
u32 *dwCmd,
|
|
u8 cmd,
|
|
u8 read,
|
|
u8 length,
|
|
u32 addr
|
|
)
|
|
{
|
|
void __iomem *regs = mvi->regs_ex - 0x10200;
|
|
u32 dwTmp;
|
|
|
|
dwTmp = ((u32)cmd << 8) | ((u32)length << 4);
|
|
if (read)
|
|
dwTmp |= SPI_CTRL_READ_94XX;
|
|
|
|
if (addr != MV_MAX_U32) {
|
|
mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
|
|
dwTmp |= SPI_ADDR_VLD_94XX;
|
|
}
|
|
|
|
*dwCmd = dwTmp;
|
|
return 0;
|
|
}
|
|
|
|
|
|
int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
|
|
{
|
|
void __iomem *regs = mvi->regs_ex - 0x10200;
|
|
mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
|
|
{
|
|
void __iomem *regs = mvi->regs_ex - 0x10200;
|
|
u32 i, dwTmp;
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
dwTmp = mr32(SPI_CTRL_REG_94XX);
|
|
if (!(dwTmp & SPI_CTRL_SpiStart_94XX))
|
|
return 0;
|
|
msleep(10);
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
#ifndef DISABLE_HOTPLUG_DMA_FIX
|
|
void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
|
|
{
|
|
int i;
|
|
struct mvs_prd *buf_prd = prd;
|
|
buf_prd += from;
|
|
for (i = 0; i < MAX_SG_ENTRY - from; i++) {
|
|
buf_prd->addr = cpu_to_le64(buf_dma);
|
|
buf_prd->im_len.len = cpu_to_le32(buf_len);
|
|
++buf_prd;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* FIXME JEJB: temporary nop clear_srs_irq to make 94xx still work
|
|
* with 64xx fixes
|
|
*/
|
|
static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set,
|
|
u8 clear_all)
|
|
{
|
|
}
|
|
|
|
const struct mvs_dispatch mvs_94xx_dispatch = {
|
|
"mv94xx",
|
|
mvs_94xx_init,
|
|
NULL,
|
|
mvs_94xx_ioremap,
|
|
mvs_94xx_iounmap,
|
|
mvs_94xx_isr,
|
|
mvs_94xx_isr_status,
|
|
mvs_94xx_interrupt_enable,
|
|
mvs_94xx_interrupt_disable,
|
|
mvs_read_phy_ctl,
|
|
mvs_write_phy_ctl,
|
|
mvs_read_port_cfg_data,
|
|
mvs_write_port_cfg_data,
|
|
mvs_write_port_cfg_addr,
|
|
mvs_read_port_vsr_data,
|
|
mvs_write_port_vsr_data,
|
|
mvs_write_port_vsr_addr,
|
|
mvs_read_port_irq_stat,
|
|
mvs_write_port_irq_stat,
|
|
mvs_read_port_irq_mask,
|
|
mvs_write_port_irq_mask,
|
|
mvs_get_sas_addr,
|
|
mvs_94xx_command_active,
|
|
mvs_94xx_clear_srs_irq,
|
|
mvs_94xx_issue_stop,
|
|
mvs_start_delivery,
|
|
mvs_rx_update,
|
|
mvs_int_full,
|
|
mvs_94xx_assign_reg_set,
|
|
mvs_94xx_free_reg_set,
|
|
mvs_get_prd_size,
|
|
mvs_get_prd_count,
|
|
mvs_94xx_make_prd,
|
|
mvs_94xx_detect_porttype,
|
|
mvs_94xx_oob_done,
|
|
mvs_94xx_fix_phy_info,
|
|
NULL,
|
|
mvs_94xx_phy_set_link_rate,
|
|
mvs_hw_max_link_rate,
|
|
mvs_94xx_phy_disable,
|
|
mvs_94xx_phy_enable,
|
|
mvs_94xx_phy_reset,
|
|
NULL,
|
|
mvs_94xx_clear_active_cmds,
|
|
mvs_94xx_spi_read_data,
|
|
mvs_94xx_spi_write_data,
|
|
mvs_94xx_spi_buildcmd,
|
|
mvs_94xx_spi_issuecmd,
|
|
mvs_94xx_spi_waitdataready,
|
|
#ifndef DISABLE_HOTPLUG_DMA_FIX
|
|
mvs_94xx_fix_dma,
|
|
#endif
|
|
};
|
|
|