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b7540d6250
Emit similar instruction sequences to commit a048a07d7f
("powerpc/64s: Add support for a store forwarding barrier at kernel
entry/exit") when encountering BPF_NOSPEC.
Mitigations are enabled depending on what the firmware advertises. In
particular, we do not gate these mitigations based on current settings,
just like in x86. Due to this, we don't need to take any action if
mitigations are enabled or disabled at runtime.
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/956570cbc191cd41f8274bed48ee757a86dac62a.1633464148.git.naveen.n.rao@linux.vnet.ibm.com
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* bpf_jit64.h: BPF JIT compiler for PPC64
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*
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* Copyright 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
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* IBM Corporation
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*/
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#ifndef _BPF_JIT64_H
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#define _BPF_JIT64_H
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#include "bpf_jit.h"
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/*
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* Stack layout:
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* Ensure the top half (upto local_tmp_var) stays consistent
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* with our redzone usage.
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*
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* [ prev sp ] <-------------
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* [ nv gpr save area ] 5*8 |
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* [ tail_call_cnt ] 8 |
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* [ local_tmp_var ] 16 |
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* fp (r31) --> [ ebpf stack space ] upto 512 |
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* [ frame header ] 32/112 |
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* sp (r1) ---> [ stack pointer ] --------------
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*/
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/* for gpr non volatile registers BPG_REG_6 to 10 */
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#define BPF_PPC_STACK_SAVE (5*8)
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/* for bpf JIT code internal usage */
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#define BPF_PPC_STACK_LOCALS 24
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/* stack frame excluding BPF stack, ensure this is quadword aligned */
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#define BPF_PPC_STACKFRAME (STACK_FRAME_MIN_SIZE + \
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BPF_PPC_STACK_LOCALS + BPF_PPC_STACK_SAVE)
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#ifndef __ASSEMBLY__
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/* BPF register usage */
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#define TMP_REG_1 (MAX_BPF_JIT_REG + 0)
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1)
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/* BPF to ppc register mappings */
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const int b2p[MAX_BPF_JIT_REG + 2] = {
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/* function return value */
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[BPF_REG_0] = 8,
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/* function arguments */
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[BPF_REG_1] = 3,
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[BPF_REG_2] = 4,
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[BPF_REG_3] = 5,
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[BPF_REG_4] = 6,
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[BPF_REG_5] = 7,
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/* non volatile registers */
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[BPF_REG_6] = 27,
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[BPF_REG_7] = 28,
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[BPF_REG_8] = 29,
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[BPF_REG_9] = 30,
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/* frame pointer aka BPF_REG_10 */
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[BPF_REG_FP] = 31,
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/* eBPF jit internal registers */
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[BPF_REG_AX] = 2,
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[TMP_REG_1] = 9,
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[TMP_REG_2] = 10
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};
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/* PPC NVR range -- update this if we ever use NVRs below r27 */
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#define BPF_PPC_NVR_MIN 27
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/*
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* WARNING: These can use TMP_REG_2 if the offset is not at word boundary,
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* so ensure that it isn't in use already.
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*/
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#define PPC_BPF_LL(r, base, i) do { \
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if ((i) % 4) { \
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EMIT(PPC_RAW_LI(b2p[TMP_REG_2], (i)));\
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EMIT(PPC_RAW_LDX(r, base, \
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b2p[TMP_REG_2])); \
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} else \
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EMIT(PPC_RAW_LD(r, base, i)); \
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} while(0)
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#define PPC_BPF_STL(r, base, i) do { \
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if ((i) % 4) { \
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EMIT(PPC_RAW_LI(b2p[TMP_REG_2], (i)));\
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EMIT(PPC_RAW_STDX(r, base, \
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b2p[TMP_REG_2])); \
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} else \
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EMIT(PPC_RAW_STD(r, base, i)); \
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} while(0)
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#define PPC_BPF_STLU(r, base, i) do { EMIT(PPC_RAW_STDU(r, base, i)); } while(0)
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#endif /* !__ASSEMBLY__ */
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#endif
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