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1e066a23e7
BIT_WIDTH field in I2S_CTL register is two bits wide, however
recent regmap field conversion patch trimmed it down to one bit.
Fix this by correcting the bit range!
Fixes: b5022a36d2
("ASoC: qcom: lpass: Use regmap_field for i2sctl and dmactl registers")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20210119174700.32639-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
182 lines
5.2 KiB
C
182 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*
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* lpass-ipq806x.c -- ALSA SoC CPU DAI driver for QTi LPASS
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* Splited out the IPQ8064 soc specific from lpass-cpu.c
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "lpass-lpaif-reg.h"
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#include "lpass.h"
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enum lpaif_i2s_ports {
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IPQ806X_LPAIF_I2S_PORT_CODEC_SPK,
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IPQ806X_LPAIF_I2S_PORT_CODEC_MIC,
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IPQ806X_LPAIF_I2S_PORT_SEC_SPK,
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IPQ806X_LPAIF_I2S_PORT_SEC_MIC,
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IPQ806X_LPAIF_I2S_PORT_MI2S,
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};
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enum lpaif_dma_channels {
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IPQ806X_LPAIF_RDMA_CHAN_MI2S,
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IPQ806X_LPAIF_RDMA_CHAN_PCM0,
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IPQ806X_LPAIF_RDMA_CHAN_PCM1,
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};
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static struct snd_soc_dai_driver ipq806x_lpass_cpu_dai_driver = {
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.id = IPQ806X_LPAIF_I2S_PORT_MI2S,
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.playback = {
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.stream_name = "lpass-cpu-playback",
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.formats = SNDRV_PCM_FMTBIT_S16 |
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SNDRV_PCM_FMTBIT_S24 |
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SNDRV_PCM_FMTBIT_S32,
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.rates = SNDRV_PCM_RATE_8000 |
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SNDRV_PCM_RATE_16000 |
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SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_48000 |
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SNDRV_PCM_RATE_96000,
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.rate_min = 8000,
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.rate_max = 96000,
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.channels_min = 1,
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.channels_max = 8,
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},
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.probe = &asoc_qcom_lpass_cpu_dai_probe,
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.ops = &asoc_qcom_lpass_cpu_dai_ops,
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};
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static int ipq806x_lpass_init(struct platform_device *pdev)
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{
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struct lpass_data *drvdata = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int ret;
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drvdata->ahbix_clk = devm_clk_get(dev, "ahbix-clk");
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if (IS_ERR(drvdata->ahbix_clk)) {
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dev_err(dev, "error getting ahbix-clk: %ld\n",
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PTR_ERR(drvdata->ahbix_clk));
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ret = PTR_ERR(drvdata->ahbix_clk);
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goto err_ahbix_clk;
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}
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ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
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if (ret) {
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dev_err(dev, "error setting rate on ahbix_clk: %d\n", ret);
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goto err_ahbix_clk;
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}
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dev_dbg(dev, "set ahbix_clk rate to %lu\n",
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clk_get_rate(drvdata->ahbix_clk));
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ret = clk_prepare_enable(drvdata->ahbix_clk);
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if (ret) {
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dev_err(dev, "error enabling ahbix_clk: %d\n", ret);
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goto err_ahbix_clk;
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}
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err_ahbix_clk:
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return ret;
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}
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static int ipq806x_lpass_exit(struct platform_device *pdev)
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{
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struct lpass_data *drvdata = platform_get_drvdata(pdev);
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clk_disable_unprepare(drvdata->ahbix_clk);
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return 0;
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}
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static int ipq806x_lpass_alloc_dma_channel(struct lpass_data *drvdata, int dir, unsigned int dai_id)
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{
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if (dir == SNDRV_PCM_STREAM_PLAYBACK)
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return IPQ806X_LPAIF_RDMA_CHAN_MI2S;
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else /* Capture currently not implemented */
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return -EINVAL;
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}
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static int ipq806x_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
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{
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return 0;
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}
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static struct lpass_variant ipq806x_data = {
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.i2sctrl_reg_base = 0x0010,
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.i2sctrl_reg_stride = 0x04,
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.i2s_ports = 5,
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.irq_reg_base = 0x3000,
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.irq_reg_stride = 0x1000,
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.irq_ports = 3,
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.rdma_reg_base = 0x6000,
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.rdma_reg_stride = 0x1000,
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.rdma_channels = 4,
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.wrdma_reg_base = 0xB000,
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.wrdma_reg_stride = 0x1000,
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.wrdma_channel_start = 5,
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.wrdma_channels = 4,
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.loopback = REG_FIELD_ID(0x0010, 15, 15, 5, 0x4),
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.spken = REG_FIELD_ID(0x0010, 14, 14, 5, 0x4),
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.spkmode = REG_FIELD_ID(0x0010, 10, 13, 5, 0x4),
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.spkmono = REG_FIELD_ID(0x0010, 9, 9, 5, 0x4),
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.micen = REG_FIELD_ID(0x0010, 8, 8, 5, 0x4),
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.micmode = REG_FIELD_ID(0x0010, 4, 7, 5, 0x4),
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.micmono = REG_FIELD_ID(0x0010, 3, 3, 5, 0x4),
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.wssrc = REG_FIELD_ID(0x0010, 2, 2, 5, 0x4),
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.bitwidth = REG_FIELD_ID(0x0010, 0, 1, 5, 0x4),
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.rdma_dyncclk = REG_FIELD_ID(0x6000, 12, 12, 4, 0x1000),
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.rdma_bursten = REG_FIELD_ID(0x6000, 11, 11, 4, 0x1000),
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.rdma_wpscnt = REG_FIELD_ID(0x6000, 8, 10, 4, 0x1000),
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.rdma_intf = REG_FIELD_ID(0x6000, 4, 7, 4, 0x1000),
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.rdma_fifowm = REG_FIELD_ID(0x6000, 1, 3, 4, 0x1000),
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.rdma_enable = REG_FIELD_ID(0x6000, 0, 0, 4, 0x1000),
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.wrdma_dyncclk = REG_FIELD_ID(0xB000, 12, 12, 4, 0x1000),
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.wrdma_bursten = REG_FIELD_ID(0xB000, 11, 11, 4, 0x1000),
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.wrdma_wpscnt = REG_FIELD_ID(0xB000, 8, 10, 4, 0x1000),
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.wrdma_intf = REG_FIELD_ID(0xB000, 4, 7, 4, 0x1000),
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.wrdma_fifowm = REG_FIELD_ID(0xB000, 1, 3, 4, 0x1000),
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.wrdma_enable = REG_FIELD_ID(0xB000, 0, 0, 4, 0x1000),
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.dai_driver = &ipq806x_lpass_cpu_dai_driver,
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.num_dai = 1,
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.dai_osr_clk_names = (const char *[]) {
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"mi2s-osr-clk",
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},
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.dai_bit_clk_names = (const char *[]) {
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"mi2s-bit-clk",
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},
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.init = ipq806x_lpass_init,
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.exit = ipq806x_lpass_exit,
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.alloc_dma_channel = ipq806x_lpass_alloc_dma_channel,
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.free_dma_channel = ipq806x_lpass_free_dma_channel,
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};
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static const struct of_device_id ipq806x_lpass_cpu_device_id[] __maybe_unused = {
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{ .compatible = "qcom,lpass-cpu", .data = &ipq806x_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, ipq806x_lpass_cpu_device_id);
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static struct platform_driver ipq806x_lpass_cpu_platform_driver = {
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.driver = {
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.name = "lpass-cpu",
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.of_match_table = of_match_ptr(ipq806x_lpass_cpu_device_id),
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},
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.probe = asoc_qcom_lpass_cpu_platform_probe,
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.remove = asoc_qcom_lpass_cpu_platform_remove,
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};
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module_platform_driver(ipq806x_lpass_cpu_platform_driver);
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MODULE_DESCRIPTION("QTi LPASS CPU Driver");
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MODULE_LICENSE("GPL v2");
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