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677379bc91
On a system with two security states, if SCR_EL3.FIQ is cleared,
non-secure IRQ priorities get shifted to fit the secure view but
priority masks aren't.
On such system, it turns out that GIC_PRIO_IRQON masks the priority of
normal interrupts, which obviously ends up in a hang.
Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
interrupts are not blocked by it.
Cc: Oleg Nesterov <oleg@redhat.com>
Fixes: bd82d4bd21 ("arm64: Fix incorrect irqflag restore for priority masking")
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[will: fixed Fixes: tag]
Signed-off-by: Will Deacon <will@kernel.org>
174 lines
3.7 KiB
C
174 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm64/include/asm/arch_gicv3.h
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*
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* Copyright (C) 2015 ARM Ltd.
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*/
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#ifndef __ASM_ARCH_GICV3_H
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#define __ASM_ARCH_GICV3_H
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#include <asm/sysreg.h>
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#ifndef __ASSEMBLY__
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/stringify.h>
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#include <asm/barrier.h>
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#include <asm/cacheflush.h>
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#define read_gicreg(r) read_sysreg_s(SYS_ ## r)
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#define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
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/*
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* Low-level accessors
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*
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* These system registers are 32 bits, but we make sure that the compiler
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* sets the GP register's most significant bits to 0 with an explicit cast.
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*/
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static inline void gic_write_eoir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
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isb();
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}
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static inline void gic_write_dir(u32 irq)
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{
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write_sysreg_s(irq, SYS_ICC_DIR_EL1);
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isb();
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}
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static inline u64 gic_read_iar_common(void)
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{
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u64 irqstat;
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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dsb(sy);
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return irqstat;
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}
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/*
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* Cavium ThunderX erratum 23154
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*
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* The gicv3 of ThunderX requires a modified version for reading the
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* IAR status to ensure data synchronization (access to icc_iar1_el1
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* is not sync'ed before and after).
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*/
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static inline u64 gic_read_iar_cavium_thunderx(void)
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{
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u64 irqstat;
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nops(8);
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irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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nops(4);
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mb();
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return irqstat;
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}
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static inline void gic_write_ctlr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_CTLR_EL1);
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isb();
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}
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static inline u32 gic_read_ctlr(void)
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{
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return read_sysreg_s(SYS_ICC_CTLR_EL1);
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}
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static inline void gic_write_grpen1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
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isb();
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}
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static inline void gic_write_sgi1r(u64 val)
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{
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write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
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}
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static inline u32 gic_read_sre(void)
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{
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return read_sysreg_s(SYS_ICC_SRE_EL1);
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}
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static inline void gic_write_sre(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_SRE_EL1);
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_BPR1_EL1);
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}
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static inline u32 gic_read_pmr(void)
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{
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return read_sysreg_s(SYS_ICC_PMR_EL1);
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}
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static inline void gic_write_pmr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_PMR_EL1);
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}
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static inline u32 gic_read_rpr(void)
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{
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return read_sysreg_s(SYS_ICC_RPR_EL1);
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}
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#define gic_read_typer(c) readq_relaxed(c)
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#define gic_write_irouter(v, c) writeq_relaxed(v, c)
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#define gic_read_lpir(c) readq_relaxed(c)
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#define gic_write_lpir(v, c) writeq_relaxed(v, c)
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#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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#define gits_read_baser(c) readq_relaxed(c)
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#define gits_write_baser(v, c) writeq_relaxed(v, c)
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#define gits_read_cbaser(c) readq_relaxed(c)
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#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
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#define gicr_read_propbaser(c) readq_relaxed(c)
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#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
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#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
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#define gicr_read_pendbaser(c) readq_relaxed(c)
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#define gits_write_vpropbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)
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static inline bool gic_prio_masking_enabled(void)
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{
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return system_uses_irq_prio_masking();
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}
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static inline void gic_pmr_mask_irqs(void)
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{
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BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
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GIC_PRIO_PSR_I_SET));
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BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
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/*
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* Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
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* and non-secure PMR accesses are not subject to the shifts that
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* are applied to IRQ priorities
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*/
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BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
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gic_write_pmr(GIC_PRIO_IRQOFF);
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}
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static inline void gic_arch_enable_irqs(void)
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{
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asm volatile ("msr daifclr, #2" : : : "memory");
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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