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099bfbfc7f
Pull drm updates from Dave Airlie:
"This is the main drm pull request for v4.2.
I've one other new driver from freescale on my radar, it's been posted
and reviewed, I'd just like to get someone to give it a last look, so
maybe I'll send it or maybe I'll leave it.
There is no major nouveau changes in here, Ben was working on
something big, and we agreed it was a bit late, there wasn't anything
else he considered urgent to merge.
There might be another msm pull for some bits that are waiting on
arm-soc, I'll see how we time it.
This touches some "of" stuff, acks are in place except for the fixes
to the build in various configs,t hat I just applied.
Summary:
New drivers:
- virtio-gpu:
KMS only pieces of driver for virtio-gpu in qemu.
This is just the first part of this driver, enough to run
unaccelerated userspace on. As qemu merges more we'll start
adding the 3D features for the virgl 3d work.
- amdgpu:
a new driver from AMD to driver their newer GPUs. (VI+)
It contains a new cleaner userspace API, and is a clean
break from radeon moving forward, that AMD are going to
concentrate on. It also contains a set of register headers
auto generated from AMD internal database.
core:
- atomic modesetting API completed, enabled by default now.
- Add support for mode_id blob to atomic ioctl to complete interface.
- bunch of Displayport MST fixes
- lots of misc fixes.
panel:
- new simple panels
- fix some long-standing build issues with bridge drivers
radeon:
- VCE1 support
- add a GPU reset counter for userspace
- lots of fixes.
amdkfd:
- H/W debugger support module
- static user-mode queues
- support killing all the waves when a process terminates
- use standard DECLARE_BITMAP
i915:
- Add Broxton support
- S3, rotation support for Skylake
- RPS booting tuning
- CPT modeset sequence fixes
- ns2501 dither support
- enable cmd parser on haswell
- cdclk handling fixes
- gen8 dynamic pte allocation
- lots of atomic conversion work
exynos:
- Add atomic modesetting support
- Add iommu support
- Consolidate drm driver initialization
- and MIC, DECON and MIPI-DSI support for exynos5433
omapdrm:
- atomic modesetting support (fixes lots of things in rewrite)
tegra:
- DP aux transaction fixes
- iommu support fix
msm:
- adreno a306 support
- various dsi bits
- various 64-bit fixes
- NV12MT support
rcar-du:
- atomic and misc fixes
sti:
- fix HDMI timing complaince
tilcdc:
- use drm component API to access tda998x driver
- fix module unloading
qxl:
- stability fixes"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (872 commits)
drm/nouveau: Pause between setting gpu to D3hot and cutting the power
drm/dp/mst: close deadlock in connector destruction.
drm: Always enable atomic API
drm/vgem: Set unique to "vgem"
of: fix a build error to of_graph_get_endpoint_by_regs function
drm/dp/mst: take lock around looking up the branch device on hpd irq
drm/dp/mst: make sure mst_primary mstb is valid in work function
of: add EXPORT_SYMBOL for of_graph_get_endpoint_by_regs
ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
drm/atomic: Don't set crtc_state->enable manually
drm/exynos: dsi: do not set TE GPIO direction by input
drm/exynos: dsi: add support for MIC driver as a bridge
drm/exynos: dsi: add support for Exynos5433
drm/exynos: dsi: make use of array for clock access
drm/exynos: dsi: make use of driver data for static values
drm/exynos: dsi: add macros for register access
drm/exynos: dsi: rename pll_clk to sclk_clk
drm/exynos: mic: add MIC driver
of: add helper for getting endpoint node of specific identifiers
drm/exynos: add Exynos5433 decon driver
...
949 lines
23 KiB
Plaintext
949 lines
23 KiB
Plaintext
/*
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* Samsung's Exynos4 SoC series common device tree source
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2010-2011 Linaro Ltd.
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* www.linaro.org
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*
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* Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
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* SoCs from Exynos4 series can include this file and provide values for SoCs
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* specfic bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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aliases {
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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i2c7 = &i2c_7;
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i2c8 = &i2c_8;
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csis0 = &csis_0;
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csis1 = &csis_1;
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fimc0 = &fimc_0;
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fimc1 = &fimc_1;
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fimc2 = &fimc_2;
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fimc3 = &fimc_3;
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serial0 = &serial_0;
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serial1 = &serial_1;
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serial2 = &serial_2;
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serial3 = &serial_3;
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};
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clock_audss: clock-controller@03810000 {
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compatible = "samsung,exynos4210-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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};
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i2s0: i2s@03830000 {
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compatible = "samsung,s5pv210-i2s";
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reg = <0x03830000 0x100>;
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clocks = <&clock_audss EXYNOS_I2S_BUS>;
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clock-names = "iis";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk0";
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dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
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dma-names = "tx", "rx", "tx-sec";
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samsung,idma-addr = <0x03000000>;
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#sound-dai-cells = <1>;
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status = "disabled";
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};
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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mipi_phy: video-phy@10020710 {
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compatible = "samsung,s5pv210-mipi-video-phy";
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#phy-cells = <1>;
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syscon = <&pmu_system_controller>;
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};
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pd_mfc: mfc-power-domain@10023C40 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C40 0x20>;
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#power-domain-cells = <0>;
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};
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pd_g3d: g3d-power-domain@10023C60 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C60 0x20>;
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#power-domain-cells = <0>;
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};
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pd_lcd0: lcd0-power-domain@10023C80 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C80 0x20>;
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#power-domain-cells = <0>;
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};
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pd_tv: tv-power-domain@10023C20 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C20 0x20>;
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#power-domain-cells = <0>;
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power-domains = <&pd_lcd0>;
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};
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pd_cam: cam-power-domain@10023C00 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023C00 0x20>;
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#power-domain-cells = <0>;
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};
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pd_gps: gps-power-domain@10023CE0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CE0 0x20>;
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#power-domain-cells = <0>;
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};
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pd_gps_alive: gps-alive-power-domain@10023D00 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023D00 0x20>;
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#power-domain-cells = <0>;
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};
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gic: interrupt-controller@10490000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
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};
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combiner: interrupt-controller@10440000 {
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compatible = "samsung,exynos4210-combiner";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0x10440000 0x1000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&combiner>;
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interrupts = <2 2>, <3 2>;
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};
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sys_reg: syscon@10010000 {
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compatible = "samsung,exynos4-sysreg", "syscon";
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reg = <0x10010000 0x400>;
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};
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pmu_system_controller: system-controller@10020000 {
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compatible = "samsung,exynos4210-pmu", "syscon";
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reg = <0x10020000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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dsi_0: dsi@11C80000 {
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compatible = "samsung,exynos4210-mipi-dsi";
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reg = <0x11C80000 0x10000>;
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interrupts = <0 79 0>;
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power-domains = <&pd_lcd0>;
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phys = <&mipi_phy 1>;
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phy-names = "dsim";
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clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
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clock-names = "bus_clk", "sclk_mipi";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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camera {
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compatible = "samsung,fimc", "simple-bus";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <1>;
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clock-output-names = "cam_a_clkout", "cam_b_clkout";
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ranges;
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fimc_0: fimc@11800000 {
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compatible = "samsung,exynos4210-fimc";
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reg = <0x11800000 0x1000>;
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interrupts = <0 84 0>;
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clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
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clock-names = "fimc", "sclk_fimc";
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power-domains = <&pd_cam>;
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samsung,sysreg = <&sys_reg>;
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iommus = <&sysmmu_fimc0>;
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status = "disabled";
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};
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fimc_1: fimc@11810000 {
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compatible = "samsung,exynos4210-fimc";
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reg = <0x11810000 0x1000>;
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interrupts = <0 85 0>;
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clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
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clock-names = "fimc", "sclk_fimc";
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power-domains = <&pd_cam>;
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samsung,sysreg = <&sys_reg>;
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iommus = <&sysmmu_fimc1>;
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status = "disabled";
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};
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fimc_2: fimc@11820000 {
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compatible = "samsung,exynos4210-fimc";
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reg = <0x11820000 0x1000>;
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interrupts = <0 86 0>;
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clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
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clock-names = "fimc", "sclk_fimc";
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power-domains = <&pd_cam>;
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samsung,sysreg = <&sys_reg>;
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iommus = <&sysmmu_fimc2>;
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status = "disabled";
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};
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fimc_3: fimc@11830000 {
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compatible = "samsung,exynos4210-fimc";
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reg = <0x11830000 0x1000>;
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interrupts = <0 87 0>;
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clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
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clock-names = "fimc", "sclk_fimc";
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power-domains = <&pd_cam>;
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samsung,sysreg = <&sys_reg>;
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iommus = <&sysmmu_fimc3>;
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status = "disabled";
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};
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csis_0: csis@11880000 {
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compatible = "samsung,exynos4210-csis";
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reg = <0x11880000 0x4000>;
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interrupts = <0 78 0>;
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clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
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clock-names = "csis", "sclk_csis";
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bus-width = <4>;
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power-domains = <&pd_cam>;
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phys = <&mipi_phy 0>;
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phy-names = "csis";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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csis_1: csis@11890000 {
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compatible = "samsung,exynos4210-csis";
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reg = <0x11890000 0x4000>;
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interrupts = <0 80 0>;
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clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
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clock-names = "csis", "sclk_csis";
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bus-width = <2>;
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power-domains = <&pd_cam>;
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phys = <&mipi_phy 2>;
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phy-names = "csis";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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watchdog: watchdog@10060000 {
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compatible = "samsung,s3c2410-wdt";
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reg = <0x10060000 0x100>;
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interrupts = <0 43 0>;
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clocks = <&clock CLK_WDT>;
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clock-names = "watchdog";
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status = "disabled";
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};
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rtc: rtc@10070000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x10070000 0x100>;
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interrupt-parent = <&pmu_system_controller>;
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interrupts = <0 44 0>, <0 45 0>;
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clocks = <&clock CLK_RTC>;
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clock-names = "rtc";
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status = "disabled";
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};
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keypad: keypad@100A0000 {
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compatible = "samsung,s5pv210-keypad";
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reg = <0x100A0000 0x100>;
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interrupts = <0 109 0>;
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clocks = <&clock CLK_KEYIF>;
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clock-names = "keypad";
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status = "disabled";
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};
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sdhci_0: sdhci@12510000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12510000 0x100>;
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interrupts = <0 73 0>;
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clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "hsmmc", "mmc_busclk.2";
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status = "disabled";
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};
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sdhci_1: sdhci@12520000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12520000 0x100>;
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interrupts = <0 74 0>;
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clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "hsmmc", "mmc_busclk.2";
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status = "disabled";
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};
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sdhci_2: sdhci@12530000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12530000 0x100>;
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interrupts = <0 75 0>;
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clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "hsmmc", "mmc_busclk.2";
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status = "disabled";
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};
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sdhci_3: sdhci@12540000 {
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compatible = "samsung,exynos4210-sdhci";
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reg = <0x12540000 0x100>;
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interrupts = <0 76 0>;
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clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
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clock-names = "hsmmc", "mmc_busclk.2";
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status = "disabled";
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};
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exynos_usbphy: exynos-usbphy@125B0000 {
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compatible = "samsung,exynos4210-usb2-phy";
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reg = <0x125B0000 0x100>;
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samsung,pmureg-phandle = <&pmu_system_controller>;
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clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
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clock-names = "phy", "ref";
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#phy-cells = <1>;
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status = "disabled";
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};
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hsotg: hsotg@12480000 {
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compatible = "samsung,s3c6400-hsotg";
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reg = <0x12480000 0x20000>;
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interrupts = <0 71 0>;
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clocks = <&clock CLK_USB_DEVICE>;
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clock-names = "otg";
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phys = <&exynos_usbphy 0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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ehci: ehci@12580000 {
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compatible = "samsung,exynos4210-ehci";
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reg = <0x12580000 0x100>;
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interrupts = <0 70 0>;
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clocks = <&clock CLK_USB_HOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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port@1 {
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reg = <1>;
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phys = <&exynos_usbphy 2>;
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status = "disabled";
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};
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port@2 {
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reg = <2>;
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phys = <&exynos_usbphy 3>;
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status = "disabled";
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};
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};
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ohci: ohci@12590000 {
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compatible = "samsung,exynos4210-ohci";
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reg = <0x12590000 0x100>;
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interrupts = <0 70 0>;
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clocks = <&clock CLK_USB_HOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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};
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i2s1: i2s@13960000 {
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compatible = "samsung,s3c6410-i2s";
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reg = <0x13960000 0x100>;
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clocks = <&clock CLK_I2S1>;
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clock-names = "iis";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk1";
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dmas = <&pdma1 12>, <&pdma1 11>;
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dma-names = "tx", "rx";
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#sound-dai-cells = <1>;
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status = "disabled";
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};
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|
|
i2s2: i2s@13970000 {
|
|
compatible = "samsung,s3c6410-i2s";
|
|
reg = <0x13970000 0x100>;
|
|
clocks = <&clock CLK_I2S2>;
|
|
clock-names = "iis";
|
|
#clock-cells = <1>;
|
|
clock-output-names = "i2s_cdclk2";
|
|
dmas = <&pdma0 14>, <&pdma0 13>;
|
|
dma-names = "tx", "rx";
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mfc: codec@13400000 {
|
|
compatible = "samsung,mfc-v5";
|
|
reg = <0x13400000 0x10000>;
|
|
interrupts = <0 94 0>;
|
|
power-domains = <&pd_mfc>;
|
|
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
|
|
clock-names = "mfc", "sclk_mfc";
|
|
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
|
|
iommu-names = "left", "right";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_0: serial@13800000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13800000 0x100>;
|
|
interrupts = <0 52 0>;
|
|
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_1: serial@13810000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13810000 0x100>;
|
|
interrupts = <0 53 0>;
|
|
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_2: serial@13820000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13820000 0x100>;
|
|
interrupts = <0 54 0>;
|
|
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial_3: serial@13830000 {
|
|
compatible = "samsung,exynos4210-uart";
|
|
reg = <0x13830000 0x100>;
|
|
interrupts = <0 55 0>;
|
|
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_0: i2c@13860000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13860000 0x100>;
|
|
interrupts = <0 58 0>;
|
|
clocks = <&clock CLK_I2C0>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@13870000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13870000 0x100>;
|
|
interrupts = <0 59 0>;
|
|
clocks = <&clock CLK_I2C1>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@13880000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13880000 0x100>;
|
|
interrupts = <0 60 0>;
|
|
clocks = <&clock CLK_I2C2>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@13890000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x13890000 0x100>;
|
|
interrupts = <0 61 0>;
|
|
clocks = <&clock CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_4: i2c@138A0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138A0000 0x100>;
|
|
interrupts = <0 62 0>;
|
|
clocks = <&clock CLK_I2C4>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_5: i2c@138B0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138B0000 0x100>;
|
|
interrupts = <0 63 0>;
|
|
clocks = <&clock CLK_I2C5>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_6: i2c@138C0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138C0000 0x100>;
|
|
interrupts = <0 64 0>;
|
|
clocks = <&clock CLK_I2C6>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_7: i2c@138D0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138D0000 0x100>;
|
|
interrupts = <0 65 0>;
|
|
clocks = <&clock CLK_I2C7>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_8: i2c@138E0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-hdmiphy-i2c";
|
|
reg = <0x138E0000 0x100>;
|
|
interrupts = <0 93 0>;
|
|
clocks = <&clock CLK_I2C_HDMI>;
|
|
clock-names = "i2c";
|
|
status = "disabled";
|
|
|
|
hdmi_i2c_phy: hdmiphy@38 {
|
|
compatible = "exynos4210-hdmiphy";
|
|
reg = <0x38>;
|
|
};
|
|
};
|
|
|
|
spi_0: spi@13920000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13920000 0x100>;
|
|
interrupts = <0 66 0>;
|
|
dmas = <&pdma0 7>, <&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@13930000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13930000 0x100>;
|
|
interrupts = <0 67 0>;
|
|
dmas = <&pdma1 7>, <&pdma1 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@13940000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13940000 0x100>;
|
|
interrupts = <0 68 0>;
|
|
dmas = <&pdma0 9>, <&pdma0 8>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@139D0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x139D0000 0x1000>;
|
|
interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
|
|
clocks = <&clock CLK_PWM>;
|
|
clock-names = "timers";
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
amba {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "arm,amba-bus";
|
|
interrupt-parent = <&gic>;
|
|
ranges;
|
|
|
|
pdma0: pdma@12680000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x12680000 0x1000>;
|
|
interrupts = <0 35 0>;
|
|
clocks = <&clock CLK_PDMA0>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
|
|
pdma1: pdma@12690000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x12690000 0x1000>;
|
|
interrupts = <0 36 0>;
|
|
clocks = <&clock CLK_PDMA1>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
|
|
mdma1: mdma@12850000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x12850000 0x1000>;
|
|
interrupts = <0 34 0>;
|
|
clocks = <&clock CLK_MDMA>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <1>;
|
|
};
|
|
};
|
|
|
|
fimd: fimd@11c00000 {
|
|
compatible = "samsung,exynos4210-fimd";
|
|
interrupt-parent = <&combiner>;
|
|
reg = <0x11c00000 0x20000>;
|
|
interrupt-names = "fifo", "vsync", "lcd_sys";
|
|
interrupts = <11 0>, <11 1>, <11 2>;
|
|
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
power-domains = <&pd_lcd0>;
|
|
iommus = <&sysmmu_fimd0>;
|
|
samsung,sysreg = <&sys_reg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu: tmu@100C0000 {
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
jpeg_codec: jpeg-codec@11840000 {
|
|
compatible = "samsung,exynos4210-jpeg";
|
|
reg = <0x11840000 0x1000>;
|
|
interrupts = <0 88 0>;
|
|
clocks = <&clock CLK_JPEG>;
|
|
clock-names = "jpeg";
|
|
power-domains = <&pd_cam>;
|
|
};
|
|
|
|
hdmi: hdmi@12D00000 {
|
|
compatible = "samsung,exynos4210-hdmi";
|
|
reg = <0x12D00000 0x70000>;
|
|
interrupts = <0 92 0>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
|
|
"mout_hdmi";
|
|
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
|
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
|
<&clock CLK_MOUT_HDMI>;
|
|
phy = <&hdmi_i2c_phy>;
|
|
power-domains = <&pd_tv>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mixer: mixer@12C10000 {
|
|
compatible = "samsung,exynos4210-mixer";
|
|
interrupts = <0 91 0>;
|
|
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
|
|
power-domains = <&pd_tv>;
|
|
iommus = <&sysmmu_tv>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_dmc0: ppmu_dmc0@106a0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x106a0000 0x2000>;
|
|
clocks = <&clock CLK_PPMUDMC0>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_dmc1: ppmu_dmc1@106b0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x106b0000 0x2000>;
|
|
clocks = <&clock CLK_PPMUDMC1>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_cpu: ppmu_cpu@106c0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x106c0000 0x2000>;
|
|
clocks = <&clock CLK_PPMUCPU>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_acp: ppmu_acp@10ae0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x106e0000 0x2000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_rightbus: ppmu_rightbus@112a0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x112a0000 0x2000>;
|
|
clocks = <&clock CLK_PPMURIGHT>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_leftbus: ppmu_leftbus0@116a0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x116a0000 0x2000>;
|
|
clocks = <&clock CLK_PPMULEFT>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_camif: ppmu_camif@11ac0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x11ac0000 0x2000>;
|
|
clocks = <&clock CLK_PPMUCAMIF>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_lcd0: ppmu_lcd0@11e40000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x11e40000 0x2000>;
|
|
clocks = <&clock CLK_PPMULCD0>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_fsys: ppmu_g3d@12630000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x12630000 0x2000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_image: ppmu_image@12aa0000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x12aa0000 0x2000>;
|
|
clocks = <&clock CLK_PPMUIMAGE>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_tv: ppmu_tv@12e40000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x12e40000 0x2000>;
|
|
clocks = <&clock CLK_PPMUTV>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_g3d: ppmu_g3d@13220000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x13220000 0x2000>;
|
|
clocks = <&clock CLK_PPMUG3D>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_mfc_left: ppmu_mfc_left@13660000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x13660000 0x2000>;
|
|
clocks = <&clock CLK_PPMUMFC_L>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
ppmu_mfc_right: ppmu_mfc_right@13670000 {
|
|
compatible = "samsung,exynos-ppmu";
|
|
reg = <0x13670000 0x2000>;
|
|
clocks = <&clock CLK_PPMUMFC_R>;
|
|
clock-names = "ppmu";
|
|
status = "disabled";
|
|
};
|
|
|
|
sysmmu_mfc_l: sysmmu@13620000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13620000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <5 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
|
|
power-domains = <&pd_mfc>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_mfc_r: sysmmu@13630000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13630000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <5 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
|
|
power-domains = <&pd_mfc>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_tv: sysmmu@12E20000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <5 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
|
|
power-domains = <&pd_tv>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimc0: sysmmu@11A20000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11A20000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
|
|
power-domains = <&pd_cam>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimc1: sysmmu@11A30000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11A30000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 3>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
|
|
power-domains = <&pd_cam>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimc2: sysmmu@11A40000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11A40000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
|
|
power-domains = <&pd_cam>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimc3: sysmmu@11A50000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11A50000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
|
|
power-domains = <&pd_cam>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_jpeg: sysmmu@11A60000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11A60000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
|
|
power-domains = <&pd_cam>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_rotator: sysmmu@12A30000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12A30000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <5 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
|
|
power-domains = <&pd_lcd0>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimd0: sysmmu@11E20000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11E20000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <5 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
|
|
power-domains = <&pd_lcd0>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
};
|