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e372aee8c2
Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost
identical to the one available in RZ/G2{L,UL}, the exception being some
core clocks as follows:
- The SD clock is composed of a mux and a divider, and the divider
has some limitations (div = 1 cannot be set if mux rate is 800MHz),
- There are 3 SD clocks,
- The OCTA and TSU clocks are specific to RZ/G3S,
- PLL1/4/6 are specific to RZ/G3S with its own computation formula.
Even with this RZ/G3S could use the same bindings as RZ/G2L.
Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse
Generator (CPG) core clocks, module clocks and resets were added.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-13-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
243 lines
7.8 KiB
C
243 lines
7.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__
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#define __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R9A08G045 CPG Core Clocks */
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#define R9A08G045_CLK_I 0
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#define R9A08G045_CLK_I2 1
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#define R9A08G045_CLK_I3 2
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#define R9A08G045_CLK_S0 3
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#define R9A08G045_CLK_SPI0 4
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#define R9A08G045_CLK_SPI1 5
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#define R9A08G045_CLK_SD0 6
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#define R9A08G045_CLK_SD1 7
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#define R9A08G045_CLK_SD2 8
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#define R9A08G045_CLK_M0 9
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#define R9A08G045_CLK_HP 10
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#define R9A08G045_CLK_TSU 11
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#define R9A08G045_CLK_ZT 12
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#define R9A08G045_CLK_P0 13
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#define R9A08G045_CLK_P1 14
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#define R9A08G045_CLK_P2 15
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#define R9A08G045_CLK_P3 16
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#define R9A08G045_CLK_P4 17
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#define R9A08G045_CLK_P5 18
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#define R9A08G045_CLK_AT 19
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#define R9A08G045_CLK_OC0 20
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#define R9A08G045_CLK_OC1 21
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#define R9A08G045_OSCCLK 22
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#define R9A08G045_OSCCLK2 23
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#define R9A08G045_SWD 24
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/* R9A08G045 Module Clocks */
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#define R9A08G045_OCTA_ACLK 0
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#define R9A08G045_OCTA_MCLK 1
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#define R9A08G045_CA55_SCLK 2
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#define R9A08G045_CA55_PCLK 3
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#define R9A08G045_CA55_ATCLK 4
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#define R9A08G045_CA55_GICCLK 5
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#define R9A08G045_CA55_PERICLK 6
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#define R9A08G045_CA55_ACLK 7
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#define R9A08G045_CA55_TSCLK 8
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#define R9A08G045_SRAM_ACPU_ACLK0 9
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#define R9A08G045_SRAM_ACPU_ACLK1 10
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#define R9A08G045_SRAM_ACPU_ACLK2 11
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#define R9A08G045_GIC600_GICCLK 12
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#define R9A08G045_IA55_CLK 13
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#define R9A08G045_IA55_PCLK 14
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#define R9A08G045_MHU_PCLK 15
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#define R9A08G045_SYC_CNT_CLK 16
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#define R9A08G045_DMAC_ACLK 17
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#define R9A08G045_DMAC_PCLK 18
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#define R9A08G045_OSTM0_PCLK 19
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#define R9A08G045_OSTM1_PCLK 20
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#define R9A08G045_OSTM2_PCLK 21
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#define R9A08G045_OSTM3_PCLK 22
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#define R9A08G045_OSTM4_PCLK 23
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#define R9A08G045_OSTM5_PCLK 24
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#define R9A08G045_OSTM6_PCLK 25
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#define R9A08G045_OSTM7_PCLK 26
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#define R9A08G045_MTU_X_MCK_MTU3 27
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#define R9A08G045_POE3_CLKM_POE 28
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#define R9A08G045_GPT_PCLK 29
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#define R9A08G045_POEG_A_CLKP 30
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#define R9A08G045_POEG_B_CLKP 31
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#define R9A08G045_POEG_C_CLKP 32
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#define R9A08G045_POEG_D_CLKP 33
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#define R9A08G045_WDT0_PCLK 34
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#define R9A08G045_WDT0_CLK 35
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#define R9A08G045_WDT1_PCLK 36
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#define R9A08G045_WDT1_CLK 37
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#define R9A08G045_WDT2_PCLK 38
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#define R9A08G045_WDT2_CLK 39
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#define R9A08G045_SPI_HCLK 40
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#define R9A08G045_SPI_ACLK 41
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#define R9A08G045_SPI_CLK 42
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#define R9A08G045_SPI_CLKX2 43
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#define R9A08G045_SDHI0_IMCLK 44
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#define R9A08G045_SDHI0_IMCLK2 45
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#define R9A08G045_SDHI0_CLK_HS 46
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#define R9A08G045_SDHI0_ACLK 47
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#define R9A08G045_SDHI1_IMCLK 48
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#define R9A08G045_SDHI1_IMCLK2 49
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#define R9A08G045_SDHI1_CLK_HS 50
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#define R9A08G045_SDHI1_ACLK 51
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#define R9A08G045_SDHI2_IMCLK 52
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#define R9A08G045_SDHI2_IMCLK2 53
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#define R9A08G045_SDHI2_CLK_HS 54
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#define R9A08G045_SDHI2_ACLK 55
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#define R9A08G045_SSI0_PCLK2 56
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#define R9A08G045_SSI0_PCLK_SFR 57
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#define R9A08G045_SSI1_PCLK2 58
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#define R9A08G045_SSI1_PCLK_SFR 59
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#define R9A08G045_SSI2_PCLK2 60
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#define R9A08G045_SSI2_PCLK_SFR 61
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#define R9A08G045_SSI3_PCLK2 62
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#define R9A08G045_SSI3_PCLK_SFR 63
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#define R9A08G045_SRC_CLKP 64
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#define R9A08G045_USB_U2H0_HCLK 65
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#define R9A08G045_USB_U2H1_HCLK 66
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#define R9A08G045_USB_U2P_EXR_CPUCLK 67
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#define R9A08G045_USB_PCLK 68
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#define R9A08G045_ETH0_CLK_AXI 69
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#define R9A08G045_ETH0_CLK_CHI 70
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#define R9A08G045_ETH0_REFCLK 71
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#define R9A08G045_ETH1_CLK_AXI 72
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#define R9A08G045_ETH1_CLK_CHI 73
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#define R9A08G045_ETH1_REFCLK 74
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#define R9A08G045_I2C0_PCLK 75
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#define R9A08G045_I2C1_PCLK 76
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#define R9A08G045_I2C2_PCLK 77
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#define R9A08G045_I2C3_PCLK 78
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#define R9A08G045_SCIF0_CLK_PCK 79
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#define R9A08G045_SCIF1_CLK_PCK 80
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#define R9A08G045_SCIF2_CLK_PCK 81
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#define R9A08G045_SCIF3_CLK_PCK 82
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#define R9A08G045_SCIF4_CLK_PCK 83
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#define R9A08G045_SCIF5_CLK_PCK 84
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#define R9A08G045_SCI0_CLKP 85
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#define R9A08G045_SCI1_CLKP 86
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#define R9A08G045_IRDA_CLKP 87
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#define R9A08G045_RSPI0_CLKB 88
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#define R9A08G045_RSPI1_CLKB 89
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#define R9A08G045_RSPI2_CLKB 90
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#define R9A08G045_RSPI3_CLKB 91
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#define R9A08G045_RSPI4_CLKB 92
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#define R9A08G045_CANFD_PCLK 93
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#define R9A08G045_CANFD_CLK_RAM 94
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#define R9A08G045_GPIO_HCLK 95
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#define R9A08G045_ADC_ADCLK 96
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#define R9A08G045_ADC_PCLK 97
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#define R9A08G045_TSU_PCLK 98
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#define R9A08G045_PDM_PCLK 99
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#define R9A08G045_PDM_CCLK 100
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#define R9A08G045_PCI_ACLK 101
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#define R9A08G045_PCI_CLKL1PM 102
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#define R9A08G045_SPDIF_PCLK 103
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#define R9A08G045_I3C_PCLK 104
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#define R9A08G045_I3C_TCLK 105
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#define R9A08G045_VBAT_BCLK 106
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/* R9A08G045 Resets */
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#define R9A08G045_CA55_RST_1_0 0
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#define R9A08G045_CA55_RST_3_0 1
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#define R9A08G045_CA55_RST_4 2
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#define R9A08G045_CA55_RST_5 3
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#define R9A08G045_CA55_RST_6 4
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#define R9A08G045_CA55_RST_7 5
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#define R9A08G045_CA55_RST_8 6
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#define R9A08G045_CA55_RST_9 7
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#define R9A08G045_CA55_RST_10 8
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#define R9A08G045_CA55_RST_11 9
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#define R9A08G045_CA55_RST_12 10
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#define R9A08G045_SRAM_ACPU_ARESETN0 11
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#define R9A08G045_SRAM_ACPU_ARESETN1 12
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#define R9A08G045_SRAM_ACPU_ARESETN2 13
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#define R9A08G045_GIC600_GICRESET_N 14
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#define R9A08G045_GIC600_DBG_GICRESET_N 15
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#define R9A08G045_IA55_RESETN 16
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#define R9A08G045_MHU_RESETN 17
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#define R9A08G045_DMAC_ARESETN 18
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#define R9A08G045_DMAC_RST_ASYNC 19
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#define R9A08G045_SYC_RESETN 20
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#define R9A08G045_OSTM0_PRESETZ 21
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#define R9A08G045_OSTM1_PRESETZ 22
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#define R9A08G045_OSTM2_PRESETZ 23
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#define R9A08G045_OSTM3_PRESETZ 24
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#define R9A08G045_OSTM4_PRESETZ 25
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#define R9A08G045_OSTM5_PRESETZ 26
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#define R9A08G045_OSTM6_PRESETZ 27
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#define R9A08G045_OSTM7_PRESETZ 28
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#define R9A08G045_MTU_X_PRESET_MTU3 29
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#define R9A08G045_POE3_RST_M_REG 30
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#define R9A08G045_GPT_RST_C 31
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#define R9A08G045_POEG_A_RST 32
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#define R9A08G045_POEG_B_RST 33
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#define R9A08G045_POEG_C_RST 34
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#define R9A08G045_POEG_D_RST 35
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#define R9A08G045_WDT0_PRESETN 36
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#define R9A08G045_WDT1_PRESETN 37
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#define R9A08G045_WDT2_PRESETN 38
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#define R9A08G045_SPI_HRESETN 39
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#define R9A08G045_SPI_ARESETN 40
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#define R9A08G045_SDHI0_IXRST 41
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#define R9A08G045_SDHI1_IXRST 42
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#define R9A08G045_SDHI2_IXRST 43
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#define R9A08G045_SSI0_RST_M2_REG 44
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#define R9A08G045_SSI1_RST_M2_REG 45
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#define R9A08G045_SSI2_RST_M2_REG 46
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#define R9A08G045_SSI3_RST_M2_REG 47
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#define R9A08G045_SRC_RST 48
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#define R9A08G045_USB_U2H0_HRESETN 49
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#define R9A08G045_USB_U2H1_HRESETN 50
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#define R9A08G045_USB_U2P_EXL_SYSRST 51
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#define R9A08G045_USB_PRESETN 52
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#define R9A08G045_ETH0_RST_HW_N 53
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#define R9A08G045_ETH1_RST_HW_N 54
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#define R9A08G045_I2C0_MRST 55
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#define R9A08G045_I2C1_MRST 56
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#define R9A08G045_I2C2_MRST 57
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#define R9A08G045_I2C3_MRST 58
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#define R9A08G045_SCIF0_RST_SYSTEM_N 59
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#define R9A08G045_SCIF1_RST_SYSTEM_N 60
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#define R9A08G045_SCIF2_RST_SYSTEM_N 61
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#define R9A08G045_SCIF3_RST_SYSTEM_N 62
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#define R9A08G045_SCIF4_RST_SYSTEM_N 63
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#define R9A08G045_SCIF5_RST_SYSTEM_N 64
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#define R9A08G045_SCI0_RST 65
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#define R9A08G045_SCI1_RST 66
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#define R9A08G045_IRDA_RST 67
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#define R9A08G045_RSPI0_RST 68
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#define R9A08G045_RSPI1_RST 69
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#define R9A08G045_RSPI2_RST 70
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#define R9A08G045_RSPI3_RST 71
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#define R9A08G045_RSPI4_RST 72
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#define R9A08G045_CANFD_RSTP_N 73
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#define R9A08G045_CANFD_RSTC_N 74
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#define R9A08G045_GPIO_RSTN 75
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#define R9A08G045_GPIO_PORT_RESETN 76
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#define R9A08G045_GPIO_SPARE_RESETN 77
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#define R9A08G045_ADC_PRESETN 78
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#define R9A08G045_ADC_ADRST_N 79
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#define R9A08G045_TSU_PRESETN 80
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#define R9A08G045_OCTA_ARESETN 81
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#define R9A08G045_PDM0_PRESETNT 82
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#define R9A08G045_PCI_ARESETN 83
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#define R9A08G045_PCI_RST_B 84
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#define R9A08G045_PCI_RST_GP_B 85
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#define R9A08G045_PCI_RST_PS_B 86
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#define R9A08G045_PCI_RST_RSM_B 87
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#define R9A08G045_PCI_RST_CFG_B 88
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#define R9A08G045_PCI_RST_LOAD_B 89
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#define R9A08G045_SPDIF_RST 90
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#define R9A08G045_I3C_TRESETN 91
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#define R9A08G045_I3C_PRESETN 92
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#define R9A08G045_VBAT_BRESETN 93
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#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
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