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657e932665
The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most of the new clocks, GDSCs, and resets already have reserved IDs but there are some resources that don't. Add the new clock from Snapdragon 670 and document the differences between the SoC parent clocks. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com
248 lines
8.8 KiB
C
248 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
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#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
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/* GCC clock registers */
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
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#define GCC_BOOT_ROM_AHB_CLK 5
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#define GCC_CAMERA_AHB_CLK 6
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#define GCC_CAMERA_AXI_CLK 7
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#define GCC_CAMERA_XO_CLK 8
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#define GCC_CE1_AHB_CLK 9
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#define GCC_CE1_AXI_CLK 10
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#define GCC_CE1_CLK 11
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
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#define GCC_CPUSS_AHB_CLK 14
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#define GCC_CPUSS_AHB_CLK_SRC 15
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#define GCC_CPUSS_RBCPR_CLK 16
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#define GCC_CPUSS_RBCPR_CLK_SRC 17
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#define GCC_DDRSS_GPU_AXI_CLK 18
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#define GCC_DISP_AHB_CLK 19
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#define GCC_DISP_AXI_CLK 20
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#define GCC_DISP_GPLL0_CLK_SRC 21
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
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#define GCC_DISP_XO_CLK 23
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#define GCC_GP1_CLK 24
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#define GCC_GP1_CLK_SRC 25
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#define GCC_GP2_CLK 26
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#define GCC_GP2_CLK_SRC 27
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#define GCC_GP3_CLK 28
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#define GCC_GP3_CLK_SRC 29
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#define GCC_GPU_CFG_AHB_CLK 30
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#define GCC_GPU_GPLL0_CLK_SRC 31
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
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#define GCC_GPU_MEMNOC_GFX_CLK 33
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#define GCC_GPU_SNOC_DVM_GFX_CLK 34
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#define GCC_MSS_AXIS2_CLK 35
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#define GCC_MSS_CFG_AHB_CLK 36
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#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
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#define GCC_MSS_MFAB_AXIS_CLK 38
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#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
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#define GCC_MSS_SNOC_AXI_CLK 40
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#define GCC_PCIE_0_AUX_CLK 41
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#define GCC_PCIE_0_AUX_CLK_SRC 42
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#define GCC_PCIE_0_CFG_AHB_CLK 43
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#define GCC_PCIE_0_CLKREF_CLK 44
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#define GCC_PCIE_0_MSTR_AXI_CLK 45
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#define GCC_PCIE_0_PIPE_CLK 46
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#define GCC_PCIE_0_SLV_AXI_CLK 47
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
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#define GCC_PCIE_1_AUX_CLK 49
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#define GCC_PCIE_1_AUX_CLK_SRC 50
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#define GCC_PCIE_1_CFG_AHB_CLK 51
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#define GCC_PCIE_1_CLKREF_CLK 52
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#define GCC_PCIE_1_MSTR_AXI_CLK 53
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#define GCC_PCIE_1_PIPE_CLK 54
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#define GCC_PCIE_1_SLV_AXI_CLK 55
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
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#define GCC_PCIE_PHY_AUX_CLK 57
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#define GCC_PCIE_PHY_REFGEN_CLK 58
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#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
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#define GCC_PDM2_CLK 60
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#define GCC_PDM2_CLK_SRC 61
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#define GCC_PDM_AHB_CLK 62
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#define GCC_PDM_XO4_CLK 63
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#define GCC_PRNG_AHB_CLK 64
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#define GCC_QMIP_CAMERA_AHB_CLK 65
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#define GCC_QMIP_DISP_AHB_CLK 66
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#define GCC_QMIP_VIDEO_AHB_CLK 67
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#define GCC_QUPV3_WRAP0_S0_CLK 68
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
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#define GCC_QUPV3_WRAP0_S1_CLK 70
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
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#define GCC_QUPV3_WRAP0_S2_CLK 72
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
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#define GCC_QUPV3_WRAP0_S3_CLK 74
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
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#define GCC_QUPV3_WRAP0_S4_CLK 76
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
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#define GCC_QUPV3_WRAP0_S5_CLK 78
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
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#define GCC_QUPV3_WRAP0_S6_CLK 80
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
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#define GCC_QUPV3_WRAP0_S7_CLK 82
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
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#define GCC_QUPV3_WRAP1_S0_CLK 84
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
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#define GCC_QUPV3_WRAP1_S1_CLK 86
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
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#define GCC_QUPV3_WRAP1_S2_CLK 88
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
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#define GCC_QUPV3_WRAP1_S3_CLK 90
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
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#define GCC_QUPV3_WRAP1_S4_CLK 92
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
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#define GCC_QUPV3_WRAP1_S5_CLK 94
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
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#define GCC_QUPV3_WRAP1_S6_CLK 96
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
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#define GCC_QUPV3_WRAP1_S7_CLK 98
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
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#define GCC_SDCC2_AHB_CLK 104
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#define GCC_SDCC2_APPS_CLK 105
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#define GCC_SDCC2_APPS_CLK_SRC 106
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#define GCC_SDCC4_AHB_CLK 107
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#define GCC_SDCC4_APPS_CLK 108
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#define GCC_SDCC4_APPS_CLK_SRC 109
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
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#define GCC_TSIF_AHB_CLK 111
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#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
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#define GCC_TSIF_REF_CLK 113
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#define GCC_TSIF_REF_CLK_SRC 114
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#define GCC_UFS_CARD_AHB_CLK 115
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#define GCC_UFS_CARD_AXI_CLK 116
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#define GCC_UFS_CARD_AXI_CLK_SRC 117
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#define GCC_UFS_CARD_CLKREF_CLK 118
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#define GCC_UFS_CARD_ICE_CORE_CLK 119
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
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#define GCC_UFS_CARD_PHY_AUX_CLK 121
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
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#define GCC_UFS_MEM_CLKREF_CLK 128
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#define GCC_UFS_PHY_AHB_CLK 129
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#define GCC_UFS_PHY_AXI_CLK 130
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#define GCC_UFS_PHY_AXI_CLK_SRC 131
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#define GCC_UFS_PHY_ICE_CORE_CLK 132
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
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#define GCC_UFS_PHY_PHY_AUX_CLK 134
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
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#define GCC_USB30_PRIM_MASTER_CLK 141
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
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#define GCC_USB30_PRIM_SLEEP_CLK 145
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#define GCC_USB30_SEC_MASTER_CLK 146
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#define GCC_USB30_SEC_MASTER_CLK_SRC 147
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
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#define GCC_USB30_SEC_SLEEP_CLK 150
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#define GCC_USB3_PRIM_CLKREF_CLK 151
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#define GCC_USB3_PRIM_PHY_AUX_CLK 152
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
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#define GCC_USB3_SEC_CLKREF_CLK 156
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#define GCC_USB3_SEC_PHY_AUX_CLK 157
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
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#define GCC_USB3_SEC_PHY_PIPE_CLK 159
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
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#define GCC_VIDEO_AHB_CLK 162
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#define GCC_VIDEO_AXI_CLK 163
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#define GCC_VIDEO_XO_CLK 164
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#define GPLL0 165
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#define GPLL0_OUT_EVEN 166
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#define GPLL0_OUT_MAIN 167
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#define GCC_GPU_IREF_CLK 168
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#define GCC_SDCC1_AHB_CLK 169
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#define GCC_SDCC1_APPS_CLK 170
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#define GCC_SDCC1_ICE_CORE_CLK 171
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#define GCC_SDCC1_APPS_CLK_SRC 172
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
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#define GCC_APC_VS_CLK 174
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#define GCC_GPU_VS_CLK 175
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#define GCC_MSS_VS_CLK 176
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#define GCC_VDDA_VS_CLK 177
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#define GCC_VDDCX_VS_CLK 178
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#define GCC_VDDMX_VS_CLK 179
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#define GCC_VS_CTRL_AHB_CLK 180
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#define GCC_VS_CTRL_CLK 181
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#define GCC_VS_CTRL_CLK_SRC 182
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#define GCC_VSENSOR_CLK_SRC 183
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#define GPLL4 184
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#define GCC_CPUSS_DVM_BUS_CLK 185
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#define GCC_CPUSS_GNOC_CLK 186
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#define GCC_QSPI_CORE_CLK_SRC 187
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#define GCC_QSPI_CORE_CLK 188
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#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
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#define GCC_LPASS_Q6_AXI_CLK 190
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#define GCC_LPASS_SWAY_CLK 191
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#define GPLL6 192
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/* GCC Resets */
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#define GCC_MMSS_BCR 0
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#define GCC_PCIE_0_BCR 1
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#define GCC_PCIE_1_BCR 2
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#define GCC_PCIE_PHY_BCR 3
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#define GCC_PDM_BCR 4
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#define GCC_PRNG_BCR 5
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#define GCC_QUPV3_WRAPPER_0_BCR 6
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#define GCC_QUPV3_WRAPPER_1_BCR 7
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#define GCC_QUSB2PHY_PRIM_BCR 8
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#define GCC_QUSB2PHY_SEC_BCR 9
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#define GCC_SDCC2_BCR 10
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#define GCC_SDCC4_BCR 11
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#define GCC_TSIF_BCR 12
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#define GCC_UFS_CARD_BCR 13
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#define GCC_UFS_PHY_BCR 14
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#define GCC_USB30_PRIM_BCR 15
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#define GCC_USB30_SEC_BCR 16
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#define GCC_USB3_PHY_PRIM_BCR 17
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#define GCC_USB3PHY_PHY_PRIM_BCR 18
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#define GCC_USB3_DP_PHY_PRIM_BCR 19
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#define GCC_USB3_PHY_SEC_BCR 20
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#define GCC_USB3PHY_PHY_SEC_BCR 21
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#define GCC_USB3_DP_PHY_SEC_BCR 22
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
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#define GCC_PCIE_0_PHY_BCR 24
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#define GCC_PCIE_1_PHY_BCR 25
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/* GCC GDSCRs */
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#define PCIE_0_GDSC 0
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#define PCIE_1_GDSC 1
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#define UFS_CARD_GDSC 2
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#define UFS_PHY_GDSC 3
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#define USB30_PRIM_GDSC 4
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#define USB30_SEC_GDSC 5
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#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
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#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
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#endif
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