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d550f6b0a7
Rename the header guard of ccu-sun8i-v3s.h from _CCU_SUN8I_H3_H_ to
_CCU_SUN8I_V3S_H_ what corresponding with the file name.
Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Wei Li <liwei391@huawei.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221108094335.3597008-1-liwei391@huawei.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
55 lines
1.2 KiB
C
55 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* Based on ccu-sun8i-h3.h, which is:
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* Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#ifndef _CCU_SUN8I_V3S_H_
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#define _CCU_SUN8I_V3S_H_
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#include <dt-bindings/clock/sun8i-v3s-ccu.h>
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#include <dt-bindings/reset/sun8i-v3s-ccu.h>
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#define CLK_PLL_CPU 0
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#define CLK_PLL_AUDIO_BASE 1
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#define CLK_PLL_AUDIO 2
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#define CLK_PLL_AUDIO_2X 3
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#define CLK_PLL_AUDIO_4X 4
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#define CLK_PLL_AUDIO_8X 5
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#define CLK_PLL_VIDEO 6
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#define CLK_PLL_VE 7
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#define CLK_PLL_DDR0 8
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#define CLK_PLL_PERIPH0 9
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#define CLK_PLL_PERIPH0_2X 10
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#define CLK_PLL_ISP 11
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#define CLK_PLL_PERIPH1 12
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/* Reserve one number for not implemented and not used PLL_DDR1 */
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/* The CPU clock is exported */
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#define CLK_AXI 15
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#define CLK_AHB1 16
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#define CLK_APB1 17
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#define CLK_APB2 18
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#define CLK_AHB2 19
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/* All the bus gates are exported */
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/* The first bunch of module clocks are exported */
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#define CLK_DRAM 58
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/* All the DRAM gates are exported */
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/* Some more module clocks are exported */
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#define CLK_MBUS 72
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/* And the GPU module clock is exported */
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#define CLK_PLL_DDR1 74
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#endif /* _CCU_SUN8I_V3S_H_ */
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