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c83e6163d8
The internal delays for the RGMII are configurable for both RX & TX. This change adds support for configuring them via device-tree (or ACPI). Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
283 lines
7.1 KiB
C
283 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* Driver for Analog Devices Industrial Ethernet PHYs
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*
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* Copyright 2019 Analog Devices Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/bitfield.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/property.h>
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#define PHY_ID_ADIN1200 0x0283bc20
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#define PHY_ID_ADIN1300 0x0283bc30
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#define ADIN1300_MII_EXT_REG_PTR 0x0010
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#define ADIN1300_MII_EXT_REG_DATA 0x0011
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#define ADIN1300_INT_MASK_REG 0x0018
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#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
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#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
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#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
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#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
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#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
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#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
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#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
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#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
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#define ADIN1300_INT_HW_IRQ_EN BIT(0)
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#define ADIN1300_INT_MASK_EN \
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(ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
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#define ADIN1300_INT_STATUS_REG 0x0019
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#define ADIN1300_GE_RGMII_CFG_REG 0xff23
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#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
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#define ADIN1300_GE_RGMII_RX_SEL(x) \
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FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
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#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
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#define ADIN1300_GE_RGMII_GTX_SEL(x) \
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FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
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#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
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#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
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#define ADIN1300_GE_RGMII_EN BIT(0)
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/* RGMII internal delay settings for rx and tx for ADIN1300 */
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#define ADIN1300_RGMII_1_60_NS 0x0001
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#define ADIN1300_RGMII_1_80_NS 0x0002
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#define ADIN1300_RGMII_2_00_NS 0x0000
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#define ADIN1300_RGMII_2_20_NS 0x0006
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#define ADIN1300_RGMII_2_40_NS 0x0007
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#define ADIN1300_GE_RMII_CFG_REG 0xff24
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#define ADIN1300_GE_RMII_EN BIT(0)
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/**
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* struct adin_cfg_reg_map - map a config value to aregister value
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* @cfg value in device configuration
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* @reg value in the register
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*/
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struct adin_cfg_reg_map {
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int cfg;
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int reg;
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};
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static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
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{ 1600, ADIN1300_RGMII_1_60_NS },
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{ 1800, ADIN1300_RGMII_1_80_NS },
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{ 2000, ADIN1300_RGMII_2_00_NS },
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{ 2200, ADIN1300_RGMII_2_20_NS },
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{ 2400, ADIN1300_RGMII_2_40_NS },
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{ },
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};
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static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
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{
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size_t i;
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for (i = 0; tbl[i].cfg; i++) {
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if (tbl[i].cfg == cfg)
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return tbl[i].reg;
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}
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return -EINVAL;
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}
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static u32 adin_get_reg_value(struct phy_device *phydev,
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const char *prop_name,
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const struct adin_cfg_reg_map *tbl,
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u32 dflt)
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{
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struct device *dev = &phydev->mdio.dev;
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u32 val;
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int rc;
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if (device_property_read_u32(dev, prop_name, &val))
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return dflt;
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rc = adin_lookup_reg_value(tbl, val);
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if (rc < 0) {
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phydev_warn(phydev,
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"Unsupported value %u for %s using default (%u)\n",
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val, prop_name, dflt);
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return dflt;
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}
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return rc;
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}
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static int adin_config_rgmii_mode(struct phy_device *phydev)
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{
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u32 val;
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int reg;
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if (!phy_interface_is_rgmii(phydev))
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return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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ADIN1300_GE_RGMII_CFG_REG,
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ADIN1300_GE_RGMII_EN);
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reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
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if (reg < 0)
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return reg;
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reg |= ADIN1300_GE_RGMII_EN;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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reg |= ADIN1300_GE_RGMII_RXID_EN;
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val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
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adin_rgmii_delays,
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ADIN1300_RGMII_2_00_NS);
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reg &= ~ADIN1300_GE_RGMII_RX_MSK;
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reg |= ADIN1300_GE_RGMII_RX_SEL(val);
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} else {
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reg &= ~ADIN1300_GE_RGMII_RXID_EN;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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reg |= ADIN1300_GE_RGMII_TXID_EN;
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val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
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adin_rgmii_delays,
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ADIN1300_RGMII_2_00_NS);
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reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
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reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
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} else {
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reg &= ~ADIN1300_GE_RGMII_TXID_EN;
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}
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return phy_write_mmd(phydev, MDIO_MMD_VEND1,
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ADIN1300_GE_RGMII_CFG_REG, reg);
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}
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static int adin_config_rmii_mode(struct phy_device *phydev)
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{
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int reg;
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if (phydev->interface != PHY_INTERFACE_MODE_RMII)
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return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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ADIN1300_GE_RMII_CFG_REG,
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ADIN1300_GE_RMII_EN);
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reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
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if (reg < 0)
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return reg;
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reg |= ADIN1300_GE_RMII_EN;
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return phy_write_mmd(phydev, MDIO_MMD_VEND1,
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ADIN1300_GE_RMII_CFG_REG, reg);
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}
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static int adin_config_init(struct phy_device *phydev)
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{
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int rc;
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rc = genphy_config_init(phydev);
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if (rc < 0)
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return rc;
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rc = adin_config_rgmii_mode(phydev);
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if (rc < 0)
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return rc;
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rc = adin_config_rmii_mode(phydev);
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if (rc < 0)
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return rc;
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phydev_dbg(phydev, "PHY is using mode '%s'\n",
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phy_modes(phydev->interface));
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return 0;
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}
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static int adin_phy_ack_intr(struct phy_device *phydev)
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{
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/* Clear pending interrupts */
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int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
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return rc < 0 ? rc : 0;
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}
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static int adin_phy_config_intr(struct phy_device *phydev)
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{
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
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ADIN1300_INT_MASK_EN);
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return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
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ADIN1300_INT_MASK_EN);
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}
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static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
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{
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struct mii_bus *bus = phydev->mdio.bus;
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int phy_addr = phydev->mdio.addr;
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int err;
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err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, regnum);
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if (err)
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return err;
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return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
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}
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static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
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u16 val)
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{
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struct mii_bus *bus = phydev->mdio.bus;
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int phy_addr = phydev->mdio.addr;
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int err;
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err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, regnum);
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if (err)
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return err;
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return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
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}
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static struct phy_driver adin_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
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.name = "ADIN1200",
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.config_init = adin_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = adin_phy_ack_intr,
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.config_intr = adin_phy_config_intr,
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.resume = genphy_resume,
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.suspend = genphy_suspend,
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.read_mmd = adin_read_mmd,
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.write_mmd = adin_write_mmd,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
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.name = "ADIN1300",
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.config_init = adin_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.ack_interrupt = adin_phy_ack_intr,
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.config_intr = adin_phy_config_intr,
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.resume = genphy_resume,
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.suspend = genphy_suspend,
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.read_mmd = adin_read_mmd,
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.write_mmd = adin_write_mmd,
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},
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};
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module_phy_driver(adin_driver);
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static struct mdio_device_id __maybe_unused adin_tbl[] = {
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{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
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{ PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, adin_tbl);
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MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
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MODULE_LICENSE("GPL");
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