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For this driver, there is nothing between nand_scan_ident() and nand_scan_tail(). They can be merged into nand_scan(). Also, nand_scan() returns an appropriate error value when it fails. Use it instead of the fixed error code -ENXIO. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
244 lines
5.6 KiB
C
244 lines
5.6 KiB
C
/*
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* drivers/mtd/nand/socrates_nand.c
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*
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* Copyright © 2008 Ilya Yanok, Emcraft Systems
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#define FPGA_NAND_CMD_MASK (0x7 << 28)
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#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
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#define FPGA_NAND_CMD_ADDR (0x1 << 28)
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#define FPGA_NAND_CMD_READ (0x2 << 28)
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#define FPGA_NAND_CMD_WRITE (0x3 << 28)
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#define FPGA_NAND_BUSY (0x1 << 15)
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#define FPGA_NAND_ENABLE (0x1 << 31)
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#define FPGA_NAND_DATA_SHIFT 16
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struct socrates_nand_host {
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struct nand_chip nand_chip;
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void __iomem *io_base;
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struct device *dev;
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};
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/**
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* socrates_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void socrates_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd_to_nand(mtd);
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struct socrates_nand_host *host = nand_get_controller_data(this);
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for (i = 0; i < len; i++) {
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out_be32(host->io_base, FPGA_NAND_ENABLE |
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FPGA_NAND_CMD_WRITE |
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(buf[i] << FPGA_NAND_DATA_SHIFT));
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}
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}
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/**
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* socrates_nand_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void socrates_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd_to_nand(mtd);
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struct socrates_nand_host *host = nand_get_controller_data(this);
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uint32_t val;
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val = FPGA_NAND_ENABLE | FPGA_NAND_CMD_READ;
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out_be32(host->io_base, val);
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for (i = 0; i < len; i++) {
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buf[i] = (in_be32(host->io_base) >>
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FPGA_NAND_DATA_SHIFT) & 0xff;
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}
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}
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/**
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* socrates_nand_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*/
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static uint8_t socrates_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t byte;
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socrates_nand_read_buf(mtd, &byte, sizeof(byte));
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return byte;
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}
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/**
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* socrates_nand_read_word - read one word from the chip
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* @mtd: MTD device structure
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*/
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static uint16_t socrates_nand_read_word(struct mtd_info *mtd)
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{
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uint16_t word;
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socrates_nand_read_buf(mtd, (uint8_t *)&word, sizeof(word));
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return word;
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}
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/*
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* Hardware specific access to control-lines
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*/
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static void socrates_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct socrates_nand_host *host = nand_get_controller_data(nand_chip);
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uint32_t val;
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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val = FPGA_NAND_CMD_COMMAND;
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else
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val = FPGA_NAND_CMD_ADDR;
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if (ctrl & NAND_NCE)
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val |= FPGA_NAND_ENABLE;
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val |= (cmd & 0xff) << FPGA_NAND_DATA_SHIFT;
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out_be32(host->io_base, val);
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}
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/*
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* Read the Device Ready pin.
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*/
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static int socrates_nand_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct socrates_nand_host *host = nand_get_controller_data(nand_chip);
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if (in_be32(host->io_base) & FPGA_NAND_BUSY)
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return 0; /* busy */
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return 1;
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}
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/*
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* Probe for the NAND device.
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*/
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static int socrates_nand_probe(struct platform_device *ofdev)
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{
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struct socrates_nand_host *host;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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int res;
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/* Allocate memory for the device structure (and zero it) */
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host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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host->io_base = of_iomap(ofdev->dev.of_node, 0);
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if (host->io_base == NULL) {
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dev_err(&ofdev->dev, "ioremap failed\n");
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return -EIO;
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}
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nand_chip = &host->nand_chip;
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mtd = nand_to_mtd(nand_chip);
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host->dev = &ofdev->dev;
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/* link the private data structures */
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nand_set_controller_data(nand_chip, host);
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nand_set_flash_node(nand_chip, ofdev->dev.of_node);
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mtd->name = "socrates_nand";
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mtd->dev.parent = &ofdev->dev;
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/*should never be accessed directly */
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nand_chip->IO_ADDR_R = (void *)0xdeadbeef;
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nand_chip->IO_ADDR_W = (void *)0xdeadbeef;
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nand_chip->cmd_ctrl = socrates_nand_cmd_ctrl;
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nand_chip->read_byte = socrates_nand_read_byte;
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nand_chip->read_word = socrates_nand_read_word;
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nand_chip->write_buf = socrates_nand_write_buf;
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nand_chip->read_buf = socrates_nand_read_buf;
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nand_chip->dev_ready = socrates_nand_device_ready;
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nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
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nand_chip->ecc.algo = NAND_ECC_HAMMING;
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/* TODO: I have no idea what real delay is. */
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nand_chip->chip_delay = 20; /* 20us command delay time */
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dev_set_drvdata(&ofdev->dev, host);
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res = nand_scan(mtd, 1);
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if (res)
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goto out;
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res = mtd_device_register(mtd, NULL, 0);
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if (!res)
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return res;
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nand_release(mtd);
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out:
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iounmap(host->io_base);
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return res;
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}
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/*
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* Remove a NAND device.
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*/
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static int socrates_nand_remove(struct platform_device *ofdev)
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{
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struct socrates_nand_host *host = dev_get_drvdata(&ofdev->dev);
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struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
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nand_release(mtd);
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iounmap(host->io_base);
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return 0;
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}
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static const struct of_device_id socrates_nand_match[] =
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{
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{
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.compatible = "abb,socrates-nand",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, socrates_nand_match);
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static struct platform_driver socrates_nand_driver = {
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.driver = {
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.name = "socrates_nand",
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.of_match_table = socrates_nand_match,
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},
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.probe = socrates_nand_probe,
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.remove = socrates_nand_remove,
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};
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module_platform_driver(socrates_nand_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ilya Yanok");
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MODULE_DESCRIPTION("NAND driver for Socrates board");
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