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aa90ac45bc
Instead of type-casting the {tx,rx}.buf all over the place while accessing them to read/write __le{32,64} from/to the firmware, let's use the existing {get,put}_unaligned_le{32,64} accessors to hide all the type cast ugliness. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
355 lines
8.0 KiB
C
355 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* System Control and Management Interface (SCMI) Clock Protocol
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*
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* Copyright (C) 2018 ARM Ltd.
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*/
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#include "common.h"
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enum scmi_clock_protocol_cmd {
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CLOCK_ATTRIBUTES = 0x3,
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CLOCK_DESCRIBE_RATES = 0x4,
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CLOCK_RATE_SET = 0x5,
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CLOCK_RATE_GET = 0x6,
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CLOCK_CONFIG_SET = 0x7,
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};
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struct scmi_msg_resp_clock_protocol_attributes {
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__le16 num_clocks;
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u8 max_async_req;
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u8 reserved;
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};
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struct scmi_msg_resp_clock_attributes {
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__le32 attributes;
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#define CLOCK_ENABLE BIT(0)
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u8 name[SCMI_MAX_STR_SIZE];
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};
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struct scmi_clock_set_config {
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__le32 id;
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__le32 attributes;
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};
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struct scmi_msg_clock_describe_rates {
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__le32 id;
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__le32 rate_index;
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};
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struct scmi_msg_resp_clock_describe_rates {
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__le32 num_rates_flags;
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#define NUM_RETURNED(x) ((x) & 0xfff)
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#define RATE_DISCRETE(x) !((x) & BIT(12))
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#define NUM_REMAINING(x) ((x) >> 16)
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struct {
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__le32 value_low;
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__le32 value_high;
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} rate[0];
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#define RATE_TO_U64(X) \
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({ \
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typeof(X) x = (X); \
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le32_to_cpu((x).value_low) | (u64)le32_to_cpu((x).value_high) << 32; \
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})
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};
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struct scmi_clock_set_rate {
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__le32 flags;
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#define CLOCK_SET_ASYNC BIT(0)
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#define CLOCK_SET_IGNORE_RESP BIT(1)
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#define CLOCK_SET_ROUND_UP BIT(2)
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#define CLOCK_SET_ROUND_AUTO BIT(3)
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__le32 id;
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__le32 value_low;
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__le32 value_high;
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};
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struct clock_info {
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int num_clocks;
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int max_async_req;
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atomic_t cur_async_req;
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struct scmi_clock_info *clk;
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};
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static int scmi_clock_protocol_attributes_get(const struct scmi_handle *handle,
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struct clock_info *ci)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_msg_resp_clock_protocol_attributes *attr;
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ret = scmi_xfer_get_init(handle, PROTOCOL_ATTRIBUTES,
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SCMI_PROTOCOL_CLOCK, 0, sizeof(*attr), &t);
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if (ret)
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return ret;
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attr = t->rx.buf;
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ret = scmi_do_xfer(handle, t);
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if (!ret) {
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ci->num_clocks = le16_to_cpu(attr->num_clocks);
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ci->max_async_req = attr->max_async_req;
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}
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int scmi_clock_attributes_get(const struct scmi_handle *handle,
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u32 clk_id, struct scmi_clock_info *clk)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_msg_resp_clock_attributes *attr;
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ret = scmi_xfer_get_init(handle, CLOCK_ATTRIBUTES, SCMI_PROTOCOL_CLOCK,
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sizeof(clk_id), sizeof(*attr), &t);
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if (ret)
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return ret;
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put_unaligned_le32(clk_id, t->tx.buf);
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attr = t->rx.buf;
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ret = scmi_do_xfer(handle, t);
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if (!ret)
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strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE);
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else
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clk->name[0] = '\0';
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int
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scmi_clock_describe_rates_get(const struct scmi_handle *handle, u32 clk_id,
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struct scmi_clock_info *clk)
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{
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u64 *rate;
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int ret, cnt;
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bool rate_discrete = false;
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u32 tot_rate_cnt = 0, rates_flag;
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u16 num_returned, num_remaining;
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struct scmi_xfer *t;
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struct scmi_msg_clock_describe_rates *clk_desc;
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struct scmi_msg_resp_clock_describe_rates *rlist;
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ret = scmi_xfer_get_init(handle, CLOCK_DESCRIBE_RATES,
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SCMI_PROTOCOL_CLOCK, sizeof(*clk_desc), 0, &t);
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if (ret)
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return ret;
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clk_desc = t->tx.buf;
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rlist = t->rx.buf;
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do {
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clk_desc->id = cpu_to_le32(clk_id);
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/* Set the number of rates to be skipped/already read */
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clk_desc->rate_index = cpu_to_le32(tot_rate_cnt);
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ret = scmi_do_xfer(handle, t);
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if (ret)
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goto err;
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rates_flag = le32_to_cpu(rlist->num_rates_flags);
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num_remaining = NUM_REMAINING(rates_flag);
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rate_discrete = RATE_DISCRETE(rates_flag);
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num_returned = NUM_RETURNED(rates_flag);
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if (tot_rate_cnt + num_returned > SCMI_MAX_NUM_RATES) {
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dev_err(handle->dev, "No. of rates > MAX_NUM_RATES");
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break;
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}
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if (!rate_discrete) {
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clk->range.min_rate = RATE_TO_U64(rlist->rate[0]);
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clk->range.max_rate = RATE_TO_U64(rlist->rate[1]);
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clk->range.step_size = RATE_TO_U64(rlist->rate[2]);
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dev_dbg(handle->dev, "Min %llu Max %llu Step %llu Hz\n",
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clk->range.min_rate, clk->range.max_rate,
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clk->range.step_size);
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break;
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}
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rate = &clk->list.rates[tot_rate_cnt];
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for (cnt = 0; cnt < num_returned; cnt++, rate++) {
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*rate = RATE_TO_U64(rlist->rate[cnt]);
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dev_dbg(handle->dev, "Rate %llu Hz\n", *rate);
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}
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tot_rate_cnt += num_returned;
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/*
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* check for both returned and remaining to avoid infinite
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* loop due to buggy firmware
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*/
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} while (num_returned && num_remaining);
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if (rate_discrete)
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clk->list.num_rates = tot_rate_cnt;
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clk->rate_discrete = rate_discrete;
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err:
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int
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scmi_clock_rate_get(const struct scmi_handle *handle, u32 clk_id, u64 *value)
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{
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int ret;
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struct scmi_xfer *t;
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ret = scmi_xfer_get_init(handle, CLOCK_RATE_GET, SCMI_PROTOCOL_CLOCK,
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sizeof(__le32), sizeof(u64), &t);
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if (ret)
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return ret;
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put_unaligned_le32(clk_id, t->tx.buf);
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ret = scmi_do_xfer(handle, t);
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if (!ret)
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*value = get_unaligned_le64(t->rx.buf);
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int scmi_clock_rate_set(const struct scmi_handle *handle, u32 clk_id,
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u64 rate)
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{
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int ret;
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u32 flags = 0;
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struct scmi_xfer *t;
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struct scmi_clock_set_rate *cfg;
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struct clock_info *ci = handle->clk_priv;
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ret = scmi_xfer_get_init(handle, CLOCK_RATE_SET, SCMI_PROTOCOL_CLOCK,
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sizeof(*cfg), 0, &t);
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if (ret)
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return ret;
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if (ci->max_async_req &&
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atomic_inc_return(&ci->cur_async_req) < ci->max_async_req)
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flags |= CLOCK_SET_ASYNC;
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cfg = t->tx.buf;
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cfg->flags = cpu_to_le32(flags);
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cfg->id = cpu_to_le32(clk_id);
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cfg->value_low = cpu_to_le32(rate & 0xffffffff);
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cfg->value_high = cpu_to_le32(rate >> 32);
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if (flags & CLOCK_SET_ASYNC)
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ret = scmi_do_xfer_with_response(handle, t);
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else
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ret = scmi_do_xfer(handle, t);
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if (ci->max_async_req)
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atomic_dec(&ci->cur_async_req);
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int
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scmi_clock_config_set(const struct scmi_handle *handle, u32 clk_id, u32 config)
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{
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int ret;
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struct scmi_xfer *t;
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struct scmi_clock_set_config *cfg;
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ret = scmi_xfer_get_init(handle, CLOCK_CONFIG_SET, SCMI_PROTOCOL_CLOCK,
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sizeof(*cfg), 0, &t);
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if (ret)
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return ret;
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cfg = t->tx.buf;
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cfg->id = cpu_to_le32(clk_id);
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cfg->attributes = cpu_to_le32(config);
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ret = scmi_do_xfer(handle, t);
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scmi_xfer_put(handle, t);
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return ret;
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}
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static int scmi_clock_enable(const struct scmi_handle *handle, u32 clk_id)
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{
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return scmi_clock_config_set(handle, clk_id, CLOCK_ENABLE);
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}
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static int scmi_clock_disable(const struct scmi_handle *handle, u32 clk_id)
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{
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return scmi_clock_config_set(handle, clk_id, 0);
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}
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static int scmi_clock_count_get(const struct scmi_handle *handle)
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{
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struct clock_info *ci = handle->clk_priv;
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return ci->num_clocks;
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}
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static const struct scmi_clock_info *
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scmi_clock_info_get(const struct scmi_handle *handle, u32 clk_id)
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{
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struct clock_info *ci = handle->clk_priv;
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struct scmi_clock_info *clk = ci->clk + clk_id;
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if (!clk->name[0])
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return NULL;
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return clk;
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}
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static struct scmi_clk_ops clk_ops = {
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.count_get = scmi_clock_count_get,
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.info_get = scmi_clock_info_get,
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.rate_get = scmi_clock_rate_get,
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.rate_set = scmi_clock_rate_set,
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.enable = scmi_clock_enable,
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.disable = scmi_clock_disable,
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};
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static int scmi_clock_protocol_init(struct scmi_handle *handle)
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{
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u32 version;
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int clkid, ret;
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struct clock_info *cinfo;
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scmi_version_get(handle, SCMI_PROTOCOL_CLOCK, &version);
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dev_dbg(handle->dev, "Clock Version %d.%d\n",
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PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
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cinfo = devm_kzalloc(handle->dev, sizeof(*cinfo), GFP_KERNEL);
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if (!cinfo)
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return -ENOMEM;
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scmi_clock_protocol_attributes_get(handle, cinfo);
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cinfo->clk = devm_kcalloc(handle->dev, cinfo->num_clocks,
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sizeof(*cinfo->clk), GFP_KERNEL);
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if (!cinfo->clk)
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return -ENOMEM;
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for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
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struct scmi_clock_info *clk = cinfo->clk + clkid;
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ret = scmi_clock_attributes_get(handle, clkid, clk);
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if (!ret)
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scmi_clock_describe_rates_get(handle, clkid, clk);
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}
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handle->clk_ops = &clk_ops;
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handle->clk_priv = cinfo;
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return 0;
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}
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static int __init scmi_clock_init(void)
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{
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return scmi_protocol_register(SCMI_PROTOCOL_CLOCK,
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&scmi_clock_protocol_init);
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}
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subsys_initcall(scmi_clock_init);
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