Jungseok Lee c79b954bf6 arm64: mm: Implement 4 levels of translation tables ... This patch implements 4 levels of translation tables since 3 levels of page tables with 4KB pages cannot support 40-bit physical address space described in [1] due to the following issue. It is a restriction that kernel logical memory map with 4KB + 3 levels (0xffffffc000000000-0xffffffffffffffff) cannot cover RAM region from 544GB to 1024GB in [1]. Specifically, ARM64 kernel fails to create mapping for this region in map_mem function since __phys_to_virt for this region reaches to address overflow. If SoC design follows the document, [1], over 32GB RAM would be placed from 544GB. Even 64GB system is supposed to use the region from 544GB to 576GB for only 32GB RAM. Naturally, it would reach to enable 4 levels of page tables to avoid hacking __virt_to_phys and __phys_to_virt. However, it is recommended 4 levels of page table should be only enabled if memory map is too sparse or there is about 512GB RAM. References ---------- [1]: Principles of ARM Memory Maps, White Paper, Issue C Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Steve Capper <steve.capper@linaro.org> [catalin.marinas@arm.com: MEMBLOCK_INITIAL_LIMIT removed, same as PUD_SIZE] [catalin.marinas@arm.com: early_ioremap_init() updated for 4 levels] [catalin.marinas@arm.com: 48-bit VA depends on BROKEN until KVM is fixed] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>		2014-07-23 15:27:40 +01:00
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cache.S	arm64: mm: use inner-shareable barriers for inner-shareable maintenance	2014-05-09 17:21:24 +01:00
context.c	arm64: Process management	2012-09-17 13:41:58 +01:00
copypage.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
dma-mapping.c	arm64: Clean up the default pgprot setting	2014-05-09 15:53:37 +01:00
extable.c	arm64: MMU fault handling and page table management	2012-09-17 13:41:57 +01:00
fault.c	arm64: mm: Implement 4 levels of translation tables	2014-07-23 15:27:40 +01:00
flush.c	arm64: mm: Make icache synchronisation logic huge page aware	2014-07-04 14:26:01 +01:00
hugetlbpage.c	hugetlb: restrict hugepage_migration_support() to x86_64	2014-06-04 16:53:51 -07:00
init.c	arm64: place initial page tables above the kernel	2014-07-10 12:36:12 +01:00
ioremap.c	arm64: mm: Implement 4 levels of translation tables	2014-07-23 15:27:40 +01:00
Makefile	arm64: mm: Optimise tlb flush logic where we have >4K granule	2014-05-09 17:00:48 +01:00
mm.h	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c	arm64: mm: Implement 4 levels of translation tables	2014-07-23 15:27:40 +01:00
pgd.c	arm64: simplify pgd_alloc	2014-02-05 10:45:07 +00:00
proc-macros.S	arm64: mm: use ubfm for dcache_line_size	2014-01-22 16:23:58 +00:00
proc.S	arm64: mm: use inner-shareable barriers for inner-shareable maintenance	2014-05-09 17:21:24 +01:00