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5b311c1519
Add a Socionext SoC specific compatible (suggested by Rob Herring). No SoC specific data are associated with the compatible strings for now, but other SoC vendors may use this IP and want to differentiate IP variants in the future. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
285 lines
7.7 KiB
C
285 lines
7.7 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include "sdhci-pltfm.h"
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/* HRS - Host Register Set (specific to Cadence) */
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#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
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#define SDHCI_CDNS_HRS04_ACK BIT(26)
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#define SDHCI_CDNS_HRS04_RD BIT(25)
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#define SDHCI_CDNS_HRS04_WR BIT(24)
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#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12
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#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
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#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
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#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
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#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
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#define SDHCI_CDNS_HRS06_TUNE_SHIFT 8
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#define SDHCI_CDNS_HRS06_TUNE_MASK 0x3f
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#define SDHCI_CDNS_HRS06_MODE_MASK 0x7
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#define SDHCI_CDNS_HRS06_MODE_SD 0x0
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#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
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#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
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/* SRS - Slot Register Set (SDHCI-compatible) */
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#define SDHCI_CDNS_SRS_BASE 0x200
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/* PHY */
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#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
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#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
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#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
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#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
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#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
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#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
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/*
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* The tuned val register is 6 bit-wide, but not the whole of the range is
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* available. The range 0-42 seems to be available (then 43 wraps around to 0)
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* but I am not quite sure if it is official. Use only 0 to 39 for safety.
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*/
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#define SDHCI_CDNS_MAX_TUNING_LOOP 40
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struct sdhci_cdns_priv {
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void __iomem *hrs_addr;
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};
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static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
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u8 addr, u8 data)
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{
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void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
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u32 tmp;
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tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
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(addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
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writel(tmp, reg);
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tmp |= SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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tmp &= ~SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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}
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static void sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
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{
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sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_HS, 4);
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sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4);
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sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9);
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sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2);
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sdhci_cdns_write_phy_reg(priv, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3);
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}
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static inline void *sdhci_cdns_priv(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return sdhci_pltfm_priv(pltfm_host);
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}
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static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
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{
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/*
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* Cadence's spec says the Timeout Clock Frequency is the same as the
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* Base Clock Frequency. Divide it by 1000 to return a value in kHz.
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*/
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return host->max_clk / 1000;
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}
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static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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u32 mode, tmp;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
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break;
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case MMC_TIMING_MMC_DDR52:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
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break;
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case MMC_TIMING_MMC_HS200:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
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break;
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case MMC_TIMING_MMC_HS400:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
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break;
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default:
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mode = SDHCI_CDNS_HRS06_MODE_SD;
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break;
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}
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/* The speed mode for eMMC is selected by HRS06 register */
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tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
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tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
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tmp |= mode;
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writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
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/* For SD, fall back to the default handler */
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if (mode == SDHCI_CDNS_HRS06_MODE_SD)
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sdhci_set_uhs_signaling(host, timing);
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}
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static const struct sdhci_ops sdhci_cdns_ops = {
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.set_clock = sdhci_set_clock,
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.get_timeout_clock = sdhci_cdns_get_timeout_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
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.ops = &sdhci_cdns_ops,
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};
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static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
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{
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
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u32 tmp;
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if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK))
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return -EINVAL;
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tmp = readl(reg);
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tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT);
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tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT;
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tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
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writel(tmp, reg);
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return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
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0, 1);
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}
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static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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int cur_streak = 0;
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int max_streak = 0;
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int end_of_streak = 0;
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int i;
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/*
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* This handler only implements the eMMC tuning that is specific to
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* this controller. Fall back to the standard method for SD timing.
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*/
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if (host->timing != MMC_TIMING_MMC_HS200)
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return sdhci_execute_tuning(mmc, opcode);
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if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
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return -EINVAL;
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for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
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if (sdhci_cdns_set_tune_val(host, i) ||
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mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
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cur_streak = 0;
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} else { /* good */
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cur_streak++;
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if (cur_streak > max_streak) {
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max_streak = cur_streak;
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end_of_streak = i;
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}
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}
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}
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if (!max_streak) {
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dev_err(mmc_dev(host->mmc), "no tuning point found\n");
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return -EIO;
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}
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return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
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}
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static int sdhci_cdns_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_cdns_priv *priv;
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struct clk *clk;
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int ret;
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv));
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if (IS_ERR(host)) {
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ret = PTR_ERR(host);
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goto disable_clk;
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}
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pltfm_host = sdhci_priv(host);
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pltfm_host->clk = clk;
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priv = sdhci_cdns_priv(host);
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priv->hrs_addr = host->ioaddr;
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host->ioaddr += SDHCI_CDNS_SRS_BASE;
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host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto free;
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sdhci_cdns_phy_init(priv);
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ret = sdhci_add_host(host);
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if (ret)
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goto free;
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return 0;
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free:
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sdhci_pltfm_free(pdev);
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disable_clk:
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clk_disable_unprepare(clk);
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return ret;
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}
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static const struct of_device_id sdhci_cdns_match[] = {
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{ .compatible = "socionext,uniphier-sd4hc" },
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{ .compatible = "cdns,sd4hc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
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static struct platform_driver sdhci_cdns_driver = {
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.driver = {
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.name = "sdhci-cdns",
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.pm = &sdhci_pltfm_pmops,
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.of_match_table = sdhci_cdns_match,
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},
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.probe = sdhci_cdns_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_cdns_driver);
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MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
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MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
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MODULE_LICENSE("GPL");
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