Giovanni Cabiddu 642a7d49c2 crypto: qat - fix access to PFVF interrupt registers for GEN4 ... The logic that detects, enables and disables pfvf interrupts was expecting a single CSR per VF. Instead, the source and mask register are two registers with a bit per VF. Due to this, the driver is reading and setting reserved CSRs and not masking the correct source of interrupts. Fix the access to the source and mask register for QAT GEN4 devices by removing the outer loop in adf_gen4_get_vf2pf_sources(), adf_gen4_enable_vf2pf_interrupts() and adf_gen4_disable_vf2pf_interrupts() and changing the helper macros ADF_4XXX_VM2PF_SOU and ADF_4XXX_VM2PF_MSK. Fixes: a9dc0d9666 ("crypto: qat - add PFVF support to the GEN4 host driver") Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Co-developed-by: Siming Wan <siming.wan@intel.com> Signed-off-by: Siming Wan <siming.wan@intel.com> Reviewed-by: Xin Zeng <xin.zeng@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Marco Chiappero <marco.chiappero@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>		2022-01-31 11:21:43 +11:00
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qat_4xxx	crypto: qat - fix a signedness bug in get_service_enabled()	2022-01-28 16:51:11 +11:00
qat_c3xxx	crypto: qat - store the ring-to-service mapping	2021-12-24 14:18:26 +11:00
qat_c3xxxvf	crypto: qat - config VFs based on ring-to-svc mapping	2021-12-24 14:18:27 +11:00
qat_c62x	crypto: qat - store the ring-to-service mapping	2021-12-24 14:18:26 +11:00
qat_c62xvf	crypto: qat - config VFs based on ring-to-svc mapping	2021-12-24 14:18:27 +11:00
qat_common	crypto: qat - fix access to PFVF interrupt registers for GEN4	2022-01-31 11:21:43 +11:00
qat_dh895xcc	crypto: qat - store the ring-to-service mapping	2021-12-24 14:18:26 +11:00
qat_dh895xccvf	crypto: qat - config VFs based on ring-to-svc mapping	2021-12-24 14:18:27 +11:00
Kconfig	crypto: qat - introduce support for PFVF block messages	2021-12-24 14:18:26 +11:00
Makefile	crypto: qat - add qat_4xxx driver	2020-11-20 14:45:34 +11:00