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c671e79d6c
There are a number of mixer controls that support negative values. They use signed values for this with different number of bits for the values. Currently they only support the positive range. This patch replaces the unsigned mixers with signed mixers to support the full range. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>
741 lines
22 KiB
C
741 lines
22 KiB
C
/*
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* linux/sound/soc/codecs/tlv320aic32x4.c
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*
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* Copyright 2011 Vista Silicon S.L.
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*
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* Author: Javier Martin <javier.martin@vista-silicon.com>
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*
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* Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pm.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/cdev.h>
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#include <linux/slab.h>
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#include <sound/tlv320aic32x4.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include "tlv320aic32x4.h"
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struct aic32x4_rate_divs {
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u32 mclk;
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u32 rate;
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u8 p_val;
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u8 pll_j;
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u16 pll_d;
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u16 dosr;
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u8 ndac;
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u8 mdac;
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u8 aosr;
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u8 nadc;
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u8 madc;
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u8 blck_N;
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};
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struct aic32x4_priv {
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struct regmap *regmap;
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u32 sysclk;
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u32 power_cfg;
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u32 micpga_routing;
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bool swapdacs;
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int rstn_gpio;
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};
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/* 0dB min, 0.5dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
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/* -63.5dB min, 0.5dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
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/* -6dB min, 1dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
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/* -12dB min, 0.5dB steps */
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static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
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static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
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SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
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AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
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SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
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AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
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tlv_driver_gain),
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SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
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AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
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tlv_driver_gain),
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SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
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AIC32X4_HPRGAIN, 6, 0x01, 1),
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SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
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AIC32X4_LORGAIN, 6, 0x01, 1),
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SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
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AIC32X4_RMICPGAVOL, 7, 0x01, 1),
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SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
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SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
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SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
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AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
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SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
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AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
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SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
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SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
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SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
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SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
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4, 0x07, 0),
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SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
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0, 0x03, 0),
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SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
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6, 0x03, 0),
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SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
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1, 0x1F, 0),
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SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
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0, 0x7F, 0),
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SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
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3, 0x1F, 0),
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SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
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3, 0x1F, 0),
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SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
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0, 0x1F, 0),
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SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
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0, 0x0F, 0),
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};
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static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 8k rate */
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{AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
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{AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
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{AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
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/* 11.025k rate */
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{AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
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{AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
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/* 16k rate */
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{AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
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{AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
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{AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
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/* 22.05k rate */
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{AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
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{AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
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{AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
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/* 32k rate */
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{AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
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{AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
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/* 44.1k rate */
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{AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
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{AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
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{AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
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/* 48k rate */
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{AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
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{AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
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{AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
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SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
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};
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static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
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SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
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};
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static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
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};
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static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
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SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
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};
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static const struct snd_kcontrol_new left_input_mixer_controls[] = {
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SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
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SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
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SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
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};
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static const struct snd_kcontrol_new right_input_mixer_controls[] = {
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SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
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SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
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SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
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};
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static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
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SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
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SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
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&hpl_output_mixer_controls[0],
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ARRAY_SIZE(hpl_output_mixer_controls)),
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SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
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&lol_output_mixer_controls[0],
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ARRAY_SIZE(lol_output_mixer_controls)),
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SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
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SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
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SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
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&hpr_output_mixer_controls[0],
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ARRAY_SIZE(hpr_output_mixer_controls)),
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SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
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&lor_output_mixer_controls[0],
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ARRAY_SIZE(lor_output_mixer_controls)),
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SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
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SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
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&left_input_mixer_controls[0],
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ARRAY_SIZE(left_input_mixer_controls)),
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SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
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&right_input_mixer_controls[0],
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ARRAY_SIZE(right_input_mixer_controls)),
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SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
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SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
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SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
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SND_SOC_DAPM_OUTPUT("HPL"),
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SND_SOC_DAPM_OUTPUT("HPR"),
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SND_SOC_DAPM_OUTPUT("LOL"),
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SND_SOC_DAPM_OUTPUT("LOR"),
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SND_SOC_DAPM_INPUT("IN1_L"),
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SND_SOC_DAPM_INPUT("IN1_R"),
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SND_SOC_DAPM_INPUT("IN2_L"),
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SND_SOC_DAPM_INPUT("IN2_R"),
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SND_SOC_DAPM_INPUT("IN3_L"),
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SND_SOC_DAPM_INPUT("IN3_R"),
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};
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static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
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/* Left Output */
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{"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
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{"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
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{"HPL Power", NULL, "HPL Output Mixer"},
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{"HPL", NULL, "HPL Power"},
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{"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
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{"LOL Power", NULL, "LOL Output Mixer"},
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{"LOL", NULL, "LOL Power"},
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/* Right Output */
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{"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
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{"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
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{"HPR Power", NULL, "HPR Output Mixer"},
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{"HPR", NULL, "HPR Power"},
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{"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
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{"LOR Power", NULL, "LOR Output Mixer"},
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{"LOR", NULL, "LOR Power"},
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/* Left input */
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{"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
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{"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
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{"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
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{"Left ADC", NULL, "Left Input Mixer"},
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/* Right Input */
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{"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
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{"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
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{"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
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{"Right ADC", NULL, "Right Input Mixer"},
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};
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static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
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{
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.selector_reg = 0,
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.selector_mask = 0xff,
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.window_start = 0,
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.window_len = 128,
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.range_min = 0,
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.range_max = AIC32X4_RMICPGAVOL,
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},
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};
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static const struct regmap_config aic32x4_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = AIC32X4_RMICPGAVOL,
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.ranges = aic32x4_regmap_pages,
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.num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
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};
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static inline int aic32x4_get_divs(int mclk, int rate)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
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if ((aic32x4_divs[i].rate == rate)
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&& (aic32x4_divs[i].mclk == mclk)) {
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return i;
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}
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}
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printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
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return -EINVAL;
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}
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static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
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switch (freq) {
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case AIC32X4_FREQ_12000000:
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case AIC32X4_FREQ_24000000:
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case AIC32X4_FREQ_25000000:
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aic32x4->sysclk = freq;
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return 0;
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}
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printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
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return -EINVAL;
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}
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static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u8 iface_reg_1;
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u8 iface_reg_2;
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u8 iface_reg_3;
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iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
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iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
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iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
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iface_reg_2 = 0;
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iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
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iface_reg_3 = iface_reg_3 & ~(1 << 3);
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/* set master/slave audio interface */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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default:
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printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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break;
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case SND_SOC_DAIFMT_DSP_A:
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iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
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iface_reg_3 |= (1 << 3); /* invert bit clock */
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iface_reg_2 = 0x01; /* add offset 1 */
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break;
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case SND_SOC_DAIFMT_DSP_B:
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iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
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iface_reg_3 |= (1 << 3); /* invert bit clock */
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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iface_reg_1 |=
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(AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
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break;
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
iface_reg_1 |=
|
|
(AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
|
|
snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
|
|
snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
|
u8 data;
|
|
int i;
|
|
|
|
i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
|
|
if (i < 0) {
|
|
printk(KERN_ERR "aic32x4: sampling rate not supported\n");
|
|
return i;
|
|
}
|
|
|
|
/* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
|
|
snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
|
|
snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
|
|
|
|
/* We will fix R value to 1 and will make P & J=K.D as varialble */
|
|
data = snd_soc_read(codec, AIC32X4_PLLPR);
|
|
data &= ~(7 << 4);
|
|
snd_soc_write(codec, AIC32X4_PLLPR,
|
|
(data | (aic32x4_divs[i].p_val << 4) | 0x01));
|
|
|
|
snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
|
|
|
|
snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
|
|
snd_soc_write(codec, AIC32X4_PLLDLSB,
|
|
(aic32x4_divs[i].pll_d & 0xff));
|
|
|
|
/* NDAC divider value */
|
|
data = snd_soc_read(codec, AIC32X4_NDAC);
|
|
data &= ~(0x7f);
|
|
snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
|
|
|
|
/* MDAC divider value */
|
|
data = snd_soc_read(codec, AIC32X4_MDAC);
|
|
data &= ~(0x7f);
|
|
snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
|
|
|
|
/* DOSR MSB & LSB values */
|
|
snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
|
|
snd_soc_write(codec, AIC32X4_DOSRLSB,
|
|
(aic32x4_divs[i].dosr & 0xff));
|
|
|
|
/* NADC divider value */
|
|
data = snd_soc_read(codec, AIC32X4_NADC);
|
|
data &= ~(0x7f);
|
|
snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
|
|
|
|
/* MADC divider value */
|
|
data = snd_soc_read(codec, AIC32X4_MADC);
|
|
data &= ~(0x7f);
|
|
snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
|
|
|
|
/* AOSR value */
|
|
snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
|
|
|
|
/* BCLK N divider */
|
|
data = snd_soc_read(codec, AIC32X4_BCLKN);
|
|
data &= ~(0x7f);
|
|
snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
|
|
|
|
data = snd_soc_read(codec, AIC32X4_IFACE1);
|
|
data = data & ~(3 << 4);
|
|
switch (params_format(params)) {
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S20_3LE:
|
|
data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
|
data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
|
|
break;
|
|
}
|
|
snd_soc_write(codec, AIC32X4_IFACE1, data);
|
|
|
|
if (params_channels(params) == 1) {
|
|
data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
|
|
} else {
|
|
if (aic32x4->swapdacs)
|
|
data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
|
|
else
|
|
data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
|
|
}
|
|
snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
|
|
data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
|
|
{
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
u8 dac_reg;
|
|
|
|
dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
|
|
if (mute)
|
|
snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
|
|
else
|
|
snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
|
|
enum snd_soc_bias_level level)
|
|
{
|
|
switch (level) {
|
|
case SND_SOC_BIAS_ON:
|
|
/* Switch on PLL */
|
|
snd_soc_update_bits(codec, AIC32X4_PLLPR,
|
|
AIC32X4_PLLEN, AIC32X4_PLLEN);
|
|
|
|
/* Switch on NDAC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_NDAC,
|
|
AIC32X4_NDACEN, AIC32X4_NDACEN);
|
|
|
|
/* Switch on MDAC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_MDAC,
|
|
AIC32X4_MDACEN, AIC32X4_MDACEN);
|
|
|
|
/* Switch on NADC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_NADC,
|
|
AIC32X4_NADCEN, AIC32X4_NADCEN);
|
|
|
|
/* Switch on MADC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_MADC,
|
|
AIC32X4_MADCEN, AIC32X4_MADCEN);
|
|
|
|
/* Switch on BCLK_N Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_BCLKN,
|
|
AIC32X4_BCLKEN, AIC32X4_BCLKEN);
|
|
break;
|
|
case SND_SOC_BIAS_PREPARE:
|
|
break;
|
|
case SND_SOC_BIAS_STANDBY:
|
|
/* Switch off PLL */
|
|
snd_soc_update_bits(codec, AIC32X4_PLLPR,
|
|
AIC32X4_PLLEN, 0);
|
|
|
|
/* Switch off NDAC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_NDAC,
|
|
AIC32X4_NDACEN, 0);
|
|
|
|
/* Switch off MDAC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_MDAC,
|
|
AIC32X4_MDACEN, 0);
|
|
|
|
/* Switch off NADC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_NADC,
|
|
AIC32X4_NADCEN, 0);
|
|
|
|
/* Switch off MADC Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_MADC,
|
|
AIC32X4_MADCEN, 0);
|
|
|
|
/* Switch off BCLK_N Divider */
|
|
snd_soc_update_bits(codec, AIC32X4_BCLKN,
|
|
AIC32X4_BCLKEN, 0);
|
|
break;
|
|
case SND_SOC_BIAS_OFF:
|
|
break;
|
|
}
|
|
codec->dapm.bias_level = level;
|
|
return 0;
|
|
}
|
|
|
|
#define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000
|
|
#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
|
|
| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
static const struct snd_soc_dai_ops aic32x4_ops = {
|
|
.hw_params = aic32x4_hw_params,
|
|
.digital_mute = aic32x4_mute,
|
|
.set_fmt = aic32x4_set_dai_fmt,
|
|
.set_sysclk = aic32x4_set_dai_sysclk,
|
|
};
|
|
|
|
static struct snd_soc_dai_driver aic32x4_dai = {
|
|
.name = "tlv320aic32x4-hifi",
|
|
.playback = {
|
|
.stream_name = "Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AIC32X4_RATES,
|
|
.formats = AIC32X4_FORMATS,},
|
|
.capture = {
|
|
.stream_name = "Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = AIC32X4_RATES,
|
|
.formats = AIC32X4_FORMATS,},
|
|
.ops = &aic32x4_ops,
|
|
.symmetric_rates = 1,
|
|
};
|
|
|
|
static int aic32x4_suspend(struct snd_soc_codec *codec)
|
|
{
|
|
aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_resume(struct snd_soc_codec *codec)
|
|
{
|
|
aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_probe(struct snd_soc_codec *codec)
|
|
{
|
|
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
|
|
u32 tmp_reg;
|
|
|
|
snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
|
|
|
|
if (gpio_is_valid(aic32x4->rstn_gpio)) {
|
|
ndelay(10);
|
|
gpio_set_value(aic32x4->rstn_gpio, 1);
|
|
}
|
|
|
|
snd_soc_write(codec, AIC32X4_RESET, 0x01);
|
|
|
|
/* Power platform configuration */
|
|
if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
|
|
snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
|
|
AIC32X4_MICBIAS_2075V);
|
|
}
|
|
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
|
|
snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
|
|
}
|
|
|
|
tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
|
|
AIC32X4_LDOCTLEN : 0;
|
|
snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
|
|
|
|
tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
|
|
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
|
|
tmp_reg |= AIC32X4_LDOIN_18_36;
|
|
}
|
|
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
|
|
tmp_reg |= AIC32X4_LDOIN2HP;
|
|
}
|
|
snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
|
|
|
|
/* Mic PGA routing */
|
|
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
|
|
snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
|
|
else
|
|
snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_CM1L_10K);
|
|
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
|
|
snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
|
|
else
|
|
snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_CM1R_10K);
|
|
|
|
aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
|
/*
|
|
* Workaround: for an unknown reason, the ADC needs to be powered up
|
|
* and down for the first capture to work properly. It seems related to
|
|
* a HW BUG or some kind of behavior not documented in the datasheet.
|
|
*/
|
|
tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
|
|
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
|
|
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
|
|
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int aic32x4_remove(struct snd_soc_codec *codec)
|
|
{
|
|
aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
|
|
.probe = aic32x4_probe,
|
|
.remove = aic32x4_remove,
|
|
.suspend = aic32x4_suspend,
|
|
.resume = aic32x4_resume,
|
|
.set_bias_level = aic32x4_set_bias_level,
|
|
|
|
.controls = aic32x4_snd_controls,
|
|
.num_controls = ARRAY_SIZE(aic32x4_snd_controls),
|
|
.dapm_widgets = aic32x4_dapm_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
|
|
.dapm_routes = aic32x4_dapm_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
|
|
};
|
|
|
|
static int aic32x4_i2c_probe(struct i2c_client *i2c,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct aic32x4_pdata *pdata = i2c->dev.platform_data;
|
|
struct aic32x4_priv *aic32x4;
|
|
int ret;
|
|
|
|
aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
|
|
GFP_KERNEL);
|
|
if (aic32x4 == NULL)
|
|
return -ENOMEM;
|
|
|
|
aic32x4->regmap = devm_regmap_init_i2c(i2c, &aic32x4_regmap);
|
|
if (IS_ERR(aic32x4->regmap))
|
|
return PTR_ERR(aic32x4->regmap);
|
|
|
|
i2c_set_clientdata(i2c, aic32x4);
|
|
|
|
if (pdata) {
|
|
aic32x4->power_cfg = pdata->power_cfg;
|
|
aic32x4->swapdacs = pdata->swapdacs;
|
|
aic32x4->micpga_routing = pdata->micpga_routing;
|
|
aic32x4->rstn_gpio = pdata->rstn_gpio;
|
|
} else {
|
|
aic32x4->power_cfg = 0;
|
|
aic32x4->swapdacs = false;
|
|
aic32x4->micpga_routing = 0;
|
|
aic32x4->rstn_gpio = -1;
|
|
}
|
|
|
|
if (gpio_is_valid(aic32x4->rstn_gpio)) {
|
|
ret = devm_gpio_request_one(&i2c->dev, aic32x4->rstn_gpio,
|
|
GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
|
|
if (ret != 0)
|
|
return ret;
|
|
}
|
|
|
|
ret = snd_soc_register_codec(&i2c->dev,
|
|
&soc_codec_dev_aic32x4, &aic32x4_dai, 1);
|
|
return ret;
|
|
}
|
|
|
|
static int aic32x4_i2c_remove(struct i2c_client *client)
|
|
{
|
|
snd_soc_unregister_codec(&client->dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id aic32x4_i2c_id[] = {
|
|
{ "tlv320aic32x4", 0 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
|
|
|
|
static struct i2c_driver aic32x4_i2c_driver = {
|
|
.driver = {
|
|
.name = "tlv320aic32x4",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = aic32x4_i2c_probe,
|
|
.remove = aic32x4_i2c_remove,
|
|
.id_table = aic32x4_i2c_id,
|
|
};
|
|
|
|
module_i2c_driver(aic32x4_i2c_driver);
|
|
|
|
MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
|
|
MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
|
|
MODULE_LICENSE("GPL");
|