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b10848e6f9
In one shot mode, sequencer automatically disables all enabled steps at the end of each cycle. (both ADC steps and TSC steps) Hence these steps need not be saved in reg_se_cache for clearing these steps at a later stage. Also, when ADC wakes up Sequencer should not be busy executing any of the config steps except for the charge step. Previously charge step was 1 ADC clock cycle and hence it was ignored. TSC steps are always disabled at the end of each conversion cycle, hence there is no need to explicitly disable TSC steps by writing 0 to REG_SE. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
381 lines
9.5 KiB
C
381 lines
9.5 KiB
C
/*
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* TI Touch Screen / ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/sched.h>
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#include <linux/mfd/ti_am335x_tscadc.h>
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static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
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{
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unsigned int val;
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regmap_read(tsadc->regmap_tscadc, reg, &val);
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return val;
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}
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static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
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unsigned int val)
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{
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regmap_write(tsadc->regmap_tscadc, reg, val);
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}
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static const struct regmap_config tscadc_regmap_config = {
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.name = "ti_tscadc",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tsadc->reg_se_cache |= val;
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if (tsadc->adc_waiting)
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wake_up(&tsadc->reg_se_wait);
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else if (!tsadc->adc_in_use)
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
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static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
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{
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DEFINE_WAIT(wait);
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u32 reg;
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reg = tscadc_readl(tsadc, REG_ADCFSM);
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if (reg & SEQ_STATUS) {
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tsadc->adc_waiting = true;
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prepare_to_wait(&tsadc->reg_se_wait, &wait,
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TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&tsadc->reg_lock);
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schedule();
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spin_lock_irq(&tsadc->reg_lock);
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finish_wait(&tsadc->reg_se_wait, &wait);
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/*
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* Sequencer should either be idle or
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* busy applying the charge step.
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*/
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reg = tscadc_readl(tsadc, REG_ADCFSM);
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WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
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tsadc->adc_waiting = false;
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}
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tsadc->adc_in_use = true;
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}
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
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{
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spin_lock_irq(&tsadc->reg_lock);
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am335x_tscadc_need_adc(tsadc);
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tscadc_writel(tsadc, REG_SE, val);
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spin_unlock_irq(&tsadc->reg_lock);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
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void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tsadc->adc_in_use = false;
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&tsadc->reg_lock, flags);
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tsadc->reg_se_cache &= ~val;
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tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
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spin_unlock_irqrestore(&tsadc->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
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static void tscadc_idle_config(struct ti_tscadc_dev *config)
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{
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unsigned int idleconfig;
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idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
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STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
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tscadc_writel(config, REG_IDLECONFIG, idleconfig);
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}
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static int ti_tscadc_probe(struct platform_device *pdev)
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{
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struct ti_tscadc_dev *tscadc;
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struct resource *res;
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struct clk *clk;
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struct device_node *node = pdev->dev.of_node;
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struct mfd_cell *cell;
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struct property *prop;
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const __be32 *cur;
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u32 val;
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int err, ctrl;
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int clock_rate;
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int tsc_wires = 0, adc_channels = 0, total_channels;
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int readouts = 0;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "Could not find valid DT data.\n");
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return -EINVAL;
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}
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node = of_get_child_by_name(pdev->dev.of_node, "tsc");
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of_property_read_u32(node, "ti,wires", &tsc_wires);
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of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
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node = of_get_child_by_name(pdev->dev.of_node, "adc");
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of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
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adc_channels++;
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if (val > 7) {
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dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
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val);
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return -EINVAL;
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}
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}
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total_channels = tsc_wires + adc_channels;
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if (total_channels > 8) {
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dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
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return -EINVAL;
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}
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if (total_channels == 0) {
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dev_err(&pdev->dev, "Need atleast one channel.\n");
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return -EINVAL;
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}
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if (readouts * 2 + 2 + adc_channels > 16) {
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dev_err(&pdev->dev, "Too many step configurations requested\n");
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return -EINVAL;
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}
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/* Allocate memory for device */
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tscadc = devm_kzalloc(&pdev->dev,
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sizeof(struct ti_tscadc_dev), GFP_KERNEL);
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if (!tscadc) {
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dev_err(&pdev->dev, "failed to allocate memory.\n");
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return -ENOMEM;
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}
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tscadc->dev = &pdev->dev;
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err = platform_get_irq(pdev, 0);
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if (err < 0) {
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dev_err(&pdev->dev, "no irq ID is specified.\n");
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goto ret;
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} else
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tscadc->irq = err;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tscadc->tscadc_base))
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return PTR_ERR(tscadc->tscadc_base);
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tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
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tscadc->tscadc_base, &tscadc_regmap_config);
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if (IS_ERR(tscadc->regmap_tscadc)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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err = PTR_ERR(tscadc->regmap_tscadc);
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goto ret;
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}
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spin_lock_init(&tscadc->reg_lock);
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init_waitqueue_head(&tscadc->reg_se_wait);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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/*
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* The TSC_ADC_Subsystem has 2 clock domains
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* OCP_CLK and ADC_CLK.
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* The ADC clock is expected to run at target of 3MHz,
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* and expected to capture 12-bit data at a rate of 200 KSPS.
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* The TSC_ADC_SS controller design assumes the OCP clock is
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* at least 6x faster than the ADC clock.
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*/
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clk = clk_get(&pdev->dev, "adc_tsc_fck");
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get TSC fck\n");
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err = PTR_ERR(clk);
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goto err_disable_clk;
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}
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clock_rate = clk_get_rate(clk);
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clk_put(clk);
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tscadc->clk_div = clock_rate / ADC_CLK;
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/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
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tscadc->clk_div--;
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tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
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/* Set the control register bits */
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ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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/* Set register bits for Idle Config Mode */
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if (tsc_wires > 0) {
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tscadc->tsc_wires = tsc_wires;
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if (tsc_wires == 5)
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ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
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else
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ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
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tscadc_idle_config(tscadc);
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}
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/* Enable the TSC module enable bit */
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ctrl |= CNTRLREG_TSCSSENB;
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tscadc_writel(tscadc, REG_CTRL, ctrl);
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tscadc->used_cells = 0;
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tscadc->tsc_cell = -1;
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tscadc->adc_cell = -1;
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/* TSC Cell */
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if (tsc_wires > 0) {
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tscadc->tsc_cell = tscadc->used_cells;
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cell = &tscadc->cells[tscadc->used_cells++];
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cell->name = "TI-am335x-tsc";
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cell->of_compatible = "ti,am3359-tsc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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}
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/* ADC Cell */
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if (adc_channels > 0) {
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tscadc->adc_cell = tscadc->used_cells;
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cell = &tscadc->cells[tscadc->used_cells++];
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cell->name = "TI-am335x-adc";
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cell->of_compatible = "ti,am3359-adc";
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cell->platform_data = &tscadc;
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cell->pdata_size = sizeof(tscadc);
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}
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err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
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tscadc->used_cells, NULL, 0, NULL);
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if (err < 0)
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goto err_disable_clk;
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device_init_wakeup(&pdev->dev, true);
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platform_set_drvdata(pdev, tscadc);
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return 0;
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err_disable_clk:
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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ret:
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return err;
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}
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static int ti_tscadc_remove(struct platform_device *pdev)
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{
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struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
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tscadc_writel(tscadc, REG_SE, 0x00);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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mfd_remove_devices(tscadc->dev);
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return 0;
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}
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#ifdef CONFIG_PM
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static int tscadc_suspend(struct device *dev)
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{
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struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
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tscadc_writel(tscadc_dev, REG_SE, 0x00);
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pm_runtime_put_sync(dev);
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return 0;
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}
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static int tscadc_resume(struct device *dev)
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{
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struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
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u32 ctrl;
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pm_runtime_get_sync(dev);
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/* context restore */
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ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
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tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
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if (tscadc_dev->tsc_cell != -1) {
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if (tscadc_dev->tsc_wires == 5)
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ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
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else
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ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
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tscadc_idle_config(tscadc_dev);
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}
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ctrl |= CNTRLREG_TSCSSENB;
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tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
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tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
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return 0;
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}
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static const struct dev_pm_ops tscadc_pm_ops = {
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.suspend = tscadc_suspend,
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.resume = tscadc_resume,
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};
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#define TSCADC_PM_OPS (&tscadc_pm_ops)
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#else
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#define TSCADC_PM_OPS NULL
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#endif
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static const struct of_device_id ti_tscadc_dt_ids[] = {
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{ .compatible = "ti,am3359-tscadc", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
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static struct platform_driver ti_tscadc_driver = {
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.driver = {
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.name = "ti_am3359-tscadc",
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.pm = TSCADC_PM_OPS,
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.of_match_table = ti_tscadc_dt_ids,
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},
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.probe = ti_tscadc_probe,
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.remove = ti_tscadc_remove,
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};
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module_platform_driver(ti_tscadc_driver);
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MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
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MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
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MODULE_LICENSE("GPL");
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