mirror of
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d3603f4c30
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200621133512.46311-1-grandmaster@al2klimov.de
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
180 lines
4.3 KiB
ReStructuredText
180 lines
4.3 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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========================================
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GPMC (General Purpose Memory Controller)
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========================================
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GPMC is an unified memory controller dedicated to interfacing external
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memory devices like
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* Asynchronous SRAM like memories and application specific integrated
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circuit devices.
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* Asynchronous, synchronous, and page mode burst NOR flash devices
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NAND flash
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* Pseudo-SRAM devices
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GPMC is found on Texas Instruments SoC's (OMAP based)
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IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
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GPMC generic timing calculation:
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================================
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GPMC has certain timings that has to be programmed for proper
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functioning of the peripheral, while peripheral has another set of
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timings. To have peripheral work with gpmc, peripheral timings has to
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be translated to the form gpmc can understand. The way it has to be
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translated depends on the connected peripheral. Also there is a
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dependency for certain gpmc timings on gpmc clock frequency. Hence a
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generic timing routine was developed to achieve above requirements.
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Generic routine provides a generic method to calculate gpmc timings
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from gpmc peripheral timings. struct gpmc_device_timings fields has to
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be updated with timings from the datasheet of the peripheral that is
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connected to gpmc. A few of the peripheral timings can be fed either
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in time or in cycles, provision to handle this scenario has been
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provided (refer struct gpmc_device_timings definition). It may so
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happen that timing as specified by peripheral datasheet is not present
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in timing structure, in this scenario, try to correlate peripheral
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timing to the one available. If that doesn't work, try to add a new
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field as required by peripheral, educate generic timing routine to
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handle it, make sure that it does not break any of the existing.
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Then there may be cases where peripheral datasheet doesn't mention
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certain fields of struct gpmc_device_timings, zero those entries.
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Generic timing routine has been verified to work properly on
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multiple onenand's and tusb6010 peripherals.
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A word of caution: generic timing routine has been developed based
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on understanding of gpmc timings, peripheral timings, available
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custom timing routines, a kind of reverse engineering without
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most of the datasheets & hardware (to be exact none of those supported
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in mainline having custom timing routine) and by simulation.
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gpmc timing dependency on peripheral timings:
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[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
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1. common
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cs_on:
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t_ceasu
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adv_on:
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t_avdasu, t_ceavd
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2. sync common
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sync_clk:
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clk
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page_burst_access:
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t_bacc
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clk_activation:
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t_ces, t_avds
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3. read async muxed
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adv_rd_off:
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t_avdp_r
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oe_on:
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t_oeasu, t_aavdh
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access:
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t_iaa, t_oe, t_ce, t_aa
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rd_cycle:
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t_rd_cycle, t_cez_r, t_oez
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4. read async non-muxed
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adv_rd_off:
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t_avdp_r
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oe_on:
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t_oeasu
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access:
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t_iaa, t_oe, t_ce, t_aa
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rd_cycle:
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t_rd_cycle, t_cez_r, t_oez
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5. read sync muxed
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adv_rd_off:
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t_avdp_r, t_avdh
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oe_on:
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t_oeasu, t_ach, cyc_aavdh_oe
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access:
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t_iaa, cyc_iaa, cyc_oe
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rd_cycle:
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t_cez_r, t_oez, t_ce_rdyz
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6. read sync non-muxed
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adv_rd_off:
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t_avdp_r
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oe_on:
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t_oeasu
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access:
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t_iaa, cyc_iaa, cyc_oe
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rd_cycle:
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t_cez_r, t_oez, t_ce_rdyz
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7. write async muxed
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adv_wr_off:
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t_avdp_w
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we_on, wr_data_mux_bus:
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t_weasu, t_aavdh, cyc_aavhd_we
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we_off:
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t_wpl
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cs_wr_off:
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t_wph
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wr_cycle:
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t_cez_w, t_wr_cycle
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8. write async non-muxed
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adv_wr_off:
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t_avdp_w
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we_on, wr_data_mux_bus:
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t_weasu
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we_off:
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t_wpl
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cs_wr_off:
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t_wph
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wr_cycle:
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t_cez_w, t_wr_cycle
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9. write sync muxed
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adv_wr_off:
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t_avdp_w, t_avdh
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we_on, wr_data_mux_bus:
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t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
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we_off:
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t_wpl, cyc_wpl
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cs_wr_off:
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t_wph
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wr_cycle:
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t_cez_w, t_ce_rdyz
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10. write sync non-muxed
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adv_wr_off:
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t_avdp_w
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we_on, wr_data_mux_bus:
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t_weasu, t_rdyo
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we_off:
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t_wpl, cyc_wpl
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cs_wr_off:
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t_wph
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wr_cycle:
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t_cez_w, t_ce_rdyz
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Note:
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Many of gpmc timings are dependent on other gpmc timings (a few
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gpmc timings purely dependent on other gpmc timings, a reason that
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some of the gpmc timings are missing above), and it will result in
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indirect dependency of peripheral timings to gpmc timings other than
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mentioned above, refer timing routine for more details. To know what
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these peripheral timings correspond to, please see explanations in
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struct gpmc_device_timings definition. And for gpmc timings refer
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IP details (link above).
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