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Previously, we use alternative mechanism to dynamically patch the CMO operations for THEAD C906/C910 during boot for performance reason. But as pointed out by Arnd, "there is already a significant cost in accessing the invalidated cache lines afterwards, which is likely going to be much higher than the cost of an indirect branch". And indeed, there's no performance difference with GMAC and EMMC per my test on Sipeed Lichee Pi 4A board. Use riscv_nonstd_cache_ops for THEAD C906/C910 CMO to simplify the alternative code, and to acchieve Arnd's goal -- "I think moving the THEAD ops at the same level as all nonstandard operations makes sense, but I'd still leave CMO as an explicit fast path that avoids the indirect branch. This seems like the right thing to do both for readability and for platforms on which the indirect branch has a noticeable overhead." Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114143338.2406-2-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
104 lines
3.1 KiB
Plaintext
104 lines
3.1 KiB
Plaintext
menu "CPU errata selection"
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config ERRATA_ANDES
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bool "Andes AX45MP errata"
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depends on RISCV_ALTERNATIVE && RISCV_SBI
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help
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All Andes errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all Andes errata. Please say "Y"
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here if your platform uses Andes CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_ANDES_CMO
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bool "Apply Andes cache management errata"
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depends on ERRATA_ANDES && ARCH_R9A07G043
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select RISCV_DMA_NONCOHERENT
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on Andes cores.
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If you don't know what to do here, say "Y".
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on RISCV_ALTERNATIVE
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_SIFIVE_CIP_453
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bool "Apply SiFive errata CIP-453"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-453 errata to add sign extension
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to the $badaddr when exception type is instruction page fault
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and instruction access fault.
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If you don't know what to do here, say "Y".
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config ERRATA_SIFIVE_CIP_1200
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bool "Apply SiFive errata CIP-1200"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-1200 errata to repalce all
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"sfence.vma addr" with "sfence.vma" to ensure that the addr
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has been flushed from TLB.
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If you don't know what to do here, say "Y".
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config ERRATA_THEAD
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bool "T-HEAD errata"
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depends on RISCV_ALTERNATIVE
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help
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All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all T-HEAD errata. Please say "Y"
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here if your platform uses T-HEAD CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_THEAD_PBMT
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bool "Apply T-Head memory type errata"
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depends on ERRATA_THEAD && 64BIT && MMU
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select RISCV_ALTERNATIVE_EARLY
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default y
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help
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This will apply the memory type errata to handle the non-standard
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memory type bits in page-table-entries on T-Head SoCs.
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If you don't know what to do here, say "Y".
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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depends on ERRATA_THEAD && MMU
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select DMA_DIRECT_REMAP
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on T-Head SoCs.
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If you don't know what to do here, say "Y".
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config ERRATA_THEAD_PMU
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bool "Apply T-Head PMU errata"
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depends on ERRATA_THEAD && RISCV_PMU_SBI
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default y
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help
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The T-Head C9xx cores implement a PMU overflow extension very
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similar to the core SSCOFPMF extension.
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This will apply the overflow errata to handle the non-standard
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behaviour via the regular SBI PMU driver and interface.
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If you don't know what to do here, say "Y".
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endmenu # "CPU errata selection"
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