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baab853229
Add userspace support for the Memory Tagging Extension introduced by
Armv8.5.
(Catalin Marinas and others)
* for-next/mte: (30 commits)
arm64: mte: Fix typo in memory tagging ABI documentation
arm64: mte: Add Memory Tagging Extension documentation
arm64: mte: Kconfig entry
arm64: mte: Save tags when hibernating
arm64: mte: Enable swap of tagged pages
mm: Add arch hooks for saving/restoring tags
fs: Handle intra-page faults in copy_mount_options()
arm64: mte: ptrace: Add NT_ARM_TAGGED_ADDR_CTRL regset
arm64: mte: ptrace: Add PTRACE_{PEEK,POKE}MTETAGS support
arm64: mte: Allow {set,get}_tagged_addr_ctrl() on non-current tasks
arm64: mte: Restore the GCR_EL1 register after a suspend
arm64: mte: Allow user control of the generated random tags via prctl()
arm64: mte: Allow user control of the tag check mode via prctl()
mm: Allow arm64 mmap(PROT_MTE) on RAM-based files
arm64: mte: Validate the PROT_MTE request via arch_validate_flags()
mm: Introduce arch_validate_flags()
arm64: mte: Add PROT_MTE support to mmap() and mprotect()
mm: Introduce arch_calc_vm_flag_bits()
arm64: mte: Tags-aware aware memcmp_pages() implementation
arm64: Avoid unnecessary clear_user_page() indirection
...
331 lines
9.0 KiB
C
331 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Based on arch/arm/include/asm/processor.h
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*
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* Copyright (C) 1995-1999 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_PROCESSOR_H
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#define __ASM_PROCESSOR_H
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#define KERNEL_DS UL(-1)
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#define USER_DS ((UL(1) << VA_BITS) - 1)
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/*
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* On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
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* no point in shifting all network buffers by 2 bytes just to make some IP
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* header fields appear aligned in memory, potentially sacrificing some DMA
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* performance on some platforms.
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*/
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#define NET_IP_ALIGN 0
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#ifndef __ASSEMBLY__
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#include <linux/build_bug.h>
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#include <linux/cache.h>
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#include <linux/init.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <linux/thread_info.h>
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#include <vdso/processor.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/kasan.h>
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#include <asm/lse.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pointer_auth.h>
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#include <asm/ptrace.h>
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#include <asm/spectre.h>
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#include <asm/types.h>
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/*
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* TASK_SIZE - the maximum size of a user space task.
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* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
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*/
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#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
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#define TASK_SIZE_64 (UL(1) << vabits_actual)
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#ifdef CONFIG_COMPAT
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#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
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/*
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* With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
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* by the compat vectors page.
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*/
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#define TASK_SIZE_32 UL(0x100000000)
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#else
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#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
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#endif /* CONFIG_ARM64_64K_PAGES */
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#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
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TASK_SIZE_32 : TASK_SIZE_64)
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#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
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TASK_SIZE_32 : TASK_SIZE_64)
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#define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
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TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
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#else
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#define TASK_SIZE TASK_SIZE_64
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#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
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#endif /* CONFIG_COMPAT */
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#ifdef CONFIG_ARM64_FORCE_52BIT
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#define STACK_TOP_MAX TASK_SIZE_64
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
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#else
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#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
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#endif /* CONFIG_ARM64_FORCE_52BIT */
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#ifdef CONFIG_COMPAT
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#define AARCH32_VECTORS_BASE 0xffff0000
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#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
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AARCH32_VECTORS_BASE : STACK_TOP_MAX)
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#else
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#define STACK_TOP STACK_TOP_MAX
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#endif /* CONFIG_COMPAT */
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#ifndef CONFIG_ARM64_FORCE_52BIT
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#define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
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DEFAULT_MAP_WINDOW)
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#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
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base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
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base)
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#endif /* CONFIG_ARM64_FORCE_52BIT */
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extern phys_addr_t arm64_dma_phys_limit;
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#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
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struct debug_info {
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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/* Have we suspended stepping by a debugger? */
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int suspended_step;
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/* Allow breakpoints and watchpoints to be disabled for this thread. */
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int bps_disabled;
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int wps_disabled;
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/* Hardware breakpoints pinned to this task. */
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struct perf_event *hbp_break[ARM_MAX_BRP];
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struct perf_event *hbp_watch[ARM_MAX_WRP];
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#endif
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};
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struct cpu_context {
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unsigned long x19;
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unsigned long x20;
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unsigned long x21;
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unsigned long x22;
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unsigned long x23;
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unsigned long x24;
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unsigned long x25;
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unsigned long x26;
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unsigned long x27;
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unsigned long x28;
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unsigned long fp;
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unsigned long sp;
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unsigned long pc;
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};
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struct thread_struct {
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struct cpu_context cpu_context; /* cpu context */
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/*
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* Whitelisted fields for hardened usercopy:
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* Maintainers must ensure manually that this contains no
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* implicit padding.
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*/
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struct {
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unsigned long tp_value; /* TLS register */
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unsigned long tp2_value;
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struct user_fpsimd_state fpsimd_state;
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} uw;
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unsigned int fpsimd_cpu;
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void *sve_state; /* SVE registers, if any */
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unsigned int sve_vl; /* SVE vector length */
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unsigned int sve_vl_onexec; /* SVE vl after next exec */
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unsigned long fault_address; /* fault info */
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unsigned long fault_code; /* ESR_EL1 value */
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struct debug_info debug; /* debugging */
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#ifdef CONFIG_ARM64_PTR_AUTH
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struct ptrauth_keys_user keys_user;
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struct ptrauth_keys_kernel keys_kernel;
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#endif
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#ifdef CONFIG_ARM64_MTE
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u64 sctlr_tcf0;
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u64 gcr_user_incl;
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#endif
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};
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static inline void arch_thread_struct_whitelist(unsigned long *offset,
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unsigned long *size)
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{
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/* Verify that there is no padding among the whitelisted fields: */
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BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
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sizeof_field(struct thread_struct, uw.tp_value) +
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sizeof_field(struct thread_struct, uw.tp2_value) +
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sizeof_field(struct thread_struct, uw.fpsimd_state));
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*offset = offsetof(struct thread_struct, uw);
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*size = sizeof_field(struct thread_struct, uw);
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}
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#ifdef CONFIG_COMPAT
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#define task_user_tls(t) \
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({ \
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unsigned long *__tls; \
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if (is_compat_thread(task_thread_info(t))) \
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__tls = &(t)->thread.uw.tp2_value; \
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else \
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__tls = &(t)->thread.uw.tp_value; \
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__tls; \
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})
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#else
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#define task_user_tls(t) (&(t)->thread.uw.tp_value)
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#endif
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/* Sync TPIDR_EL0 back to thread_struct for current */
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void tls_preserve_current_state(void);
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#define INIT_THREAD { \
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.fpsimd_cpu = NR_CPUS, \
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}
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static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
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{
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memset(regs, 0, sizeof(*regs));
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forget_syscall(regs);
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regs->pc = pc;
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if (system_uses_irq_prio_masking())
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regs->pmr_save = GIC_PRIO_IRQON;
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}
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static inline void start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = PSR_MODE_EL0t;
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spectre_v4_enable_task_mitigation(current);
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regs->sp = sp;
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}
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#ifdef CONFIG_COMPAT
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static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
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unsigned long sp)
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{
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start_thread_common(regs, pc);
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regs->pstate = PSR_AA32_MODE_USR;
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if (pc & 1)
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regs->pstate |= PSR_AA32_T_BIT;
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#ifdef __AARCH64EB__
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regs->pstate |= PSR_AA32_E_BIT;
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#endif
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spectre_v4_enable_task_mitigation(current);
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regs->compat_sp = sp;
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}
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#endif
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static inline bool is_ttbr0_addr(unsigned long addr)
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{
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/* entry assembly clears tags for TTBR0 addrs */
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return addr < TASK_SIZE;
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}
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static inline bool is_ttbr1_addr(unsigned long addr)
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{
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/* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
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return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
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}
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/* Forward declaration, a strange C thing */
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struct task_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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unsigned long get_wchan(struct task_struct *p);
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/* Thread switching */
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extern struct task_struct *cpu_switch_to(struct task_struct *prev,
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struct task_struct *next);
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#define task_pt_regs(p) \
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((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
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#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
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#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
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/*
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* Prefetching support
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*/
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *ptr)
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{
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asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_PREFETCHW
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static inline void prefetchw(const void *ptr)
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{
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asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
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}
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void spin_lock_prefetch(const void *ptr)
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{
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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"prfm pstl1strm, %a0",
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"nop") : : "p" (ptr));
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}
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extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
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extern void __init minsigstksz_setup(void);
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/*
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* Not at the top of the file due to a direct #include cycle between
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* <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
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* ensures that contents of processor.h are visible to fpsimd.h even if
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* processor.h is included first.
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*
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* These prctl helpers are the only things in this file that require
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* fpsimd.h. The core code expects them to be in this header.
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*/
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#include <asm/fpsimd.h>
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/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
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#define SVE_SET_VL(arg) sve_set_current_vl(arg)
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#define SVE_GET_VL() sve_get_current_vl()
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/* PR_PAC_RESET_KEYS prctl */
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#define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
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#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
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/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
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long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
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long get_tagged_addr_ctrl(struct task_struct *task);
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#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
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#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
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#endif
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/*
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* For CONFIG_GCC_PLUGIN_STACKLEAK
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*
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* These need to be macros because otherwise we get stuck in a nightmare
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* of header definitions for the use of task_stack_page.
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*/
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#define current_top_of_stack() \
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({ \
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struct stack_info _info; \
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BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info)); \
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_info.high; \
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})
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#define on_thread_stack() (on_task_stack(current, current_stack_pointer, NULL))
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PROCESSOR_H */
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