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9ef2b48be9
Patching the EL2 exception vectors is integral to the Spectre-v2 workaround, where it can be necessary to execute CPU-specific sequences to nobble the branch predictor before running the hypervisor text proper. Remove the dependency on CONFIG_RANDOMIZE_BASE and allow the EL2 vectors to be patched even when KASLR is not enabled. Fixes: 7a132017e7a5 ("KVM: arm64: Replace CONFIG_KVM_INDIRECT_VECTORS with CONFIG_RANDOMIZE_BASE") Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/202009221053.Jv1XsQUZ%lkp@intel.com Signed-off-by: Will Deacon <will@kernel.org>
536 lines
15 KiB
C
536 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_MMU_H__
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#define __ARM64_KVM_MMU_H__
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#include <asm/page.h>
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#include <asm/memory.h>
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#include <asm/mmu.h>
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#include <asm/cpufeature.h>
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/*
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* As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
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* "negative" addresses. This makes it impossible to directly share
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* mappings with the kernel.
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*
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* Instead, give the HYP mode its own VA region at a fixed offset from
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* the kernel by just masking the top bits (which are all ones for a
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* kernel address). We need to find out how many bits to mask.
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*
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* We want to build a set of page tables that cover both parts of the
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* idmap (the trampoline page used to initialize EL2), and our normal
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* runtime VA space, at the same time.
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*
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* Given that the kernel uses VA_BITS for its entire address space,
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* and that half of that space (VA_BITS - 1) is used for the linear
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* mapping, we can also limit the EL2 space to (VA_BITS - 1).
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*
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* The main question is "Within the VA_BITS space, does EL2 use the
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* top or the bottom half of that space to shadow the kernel's linear
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* mapping?". As we need to idmap the trampoline page, this is
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* determined by the range in which this page lives.
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*
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* If the page is in the bottom half, we have to use the top half. If
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* the page is in the top half, we have to use the bottom half:
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*
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* T = __pa_symbol(__hyp_idmap_text_start)
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* if (T & BIT(VA_BITS - 1))
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* HYP_VA_MIN = 0 //idmap in upper half
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* else
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* HYP_VA_MIN = 1 << (VA_BITS - 1)
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* HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
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*
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* This of course assumes that the trampoline page exists within the
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* VA_BITS range. If it doesn't, then it means we're in the odd case
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* where the kernel idmap (as well as HYP) uses more levels than the
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* kernel runtime page tables (as seen when the kernel is configured
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* for 4k pages, 39bits VA, and yet memory lives just above that
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* limit, forcing the idmap to use 4 levels of page tables while the
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* kernel itself only uses 3). In this particular case, it doesn't
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* matter which side of VA_BITS we use, as we're guaranteed not to
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* conflict with anything.
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*
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* When using VHE, there are no separate hyp mappings and all KVM
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* functionality is already mapped as part of the main kernel
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* mappings, and none of this applies in that case.
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*/
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#ifdef __ASSEMBLY__
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#include <asm/alternative.h>
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/*
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* Convert a kernel VA into a HYP VA.
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* reg: VA to be converted.
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*
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* The actual code generation takes place in kvm_update_va_mask, and
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* the instructions below are only there to reserve the space and
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* perform the register allocation (kvm_update_va_mask uses the
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* specific registers encoded in the instructions).
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*/
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.macro kern_hyp_va reg
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alternative_cb kvm_update_va_mask
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and \reg, \reg, #1 /* mask with va_mask */
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ror \reg, \reg, #1 /* rotate to the first tag bit */
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add \reg, \reg, #0 /* insert the low 12 bits of the tag */
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add \reg, \reg, #0, lsl 12 /* insert the top 12 bits of the tag */
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ror \reg, \reg, #63 /* rotate back */
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alternative_cb_end
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.endm
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#else
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#include <linux/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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void kvm_update_va_mask(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr, int nr_inst);
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void kvm_compute_layout(void);
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static __always_inline unsigned long __kern_hyp_va(unsigned long v)
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{
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asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
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"ror %0, %0, #1\n"
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"add %0, %0, #0\n"
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"add %0, %0, #0, lsl 12\n"
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"ror %0, %0, #63\n",
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kvm_update_va_mask)
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: "+r" (v));
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return v;
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}
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#define kern_hyp_va(v) ((typeof(v))(__kern_hyp_va((unsigned long)(v))))
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/*
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* We currently support using a VM-specified IPA size. For backward
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* compatibility, the default IPA size is fixed to 40bits.
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*/
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#define KVM_PHYS_SHIFT (40)
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#define kvm_phys_shift(kvm) VTCR_EL2_IPA(kvm->arch.vtcr)
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#define kvm_phys_size(kvm) (_AC(1, ULL) << kvm_phys_shift(kvm))
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#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - _AC(1, ULL))
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static inline bool kvm_page_empty(void *ptr)
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{
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struct page *ptr_page = virt_to_page(ptr);
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return page_count(ptr_page) == 1;
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}
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#include <asm/stage2_pgtable.h>
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int create_hyp_mappings(void *from, void *to, pgprot_t prot);
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int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
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void __iomem **kaddr,
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void __iomem **haddr);
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int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
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void **haddr);
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void free_hyp_pgds(void);
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void stage2_unmap_vm(struct kvm *kvm);
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int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s2_mmu *mmu);
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void kvm_free_stage2_pgd(struct kvm_s2_mmu *mmu);
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int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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phys_addr_t pa, unsigned long size, bool writable);
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int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
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void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
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phys_addr_t kvm_mmu_get_httbr(void);
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phys_addr_t kvm_get_idmap_vector(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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#define kvm_mk_pmd(ptep) \
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__pmd(__phys_to_pmd_val(__pa(ptep)) | PMD_TYPE_TABLE)
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#define kvm_mk_pud(pmdp) \
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__pud(__phys_to_pud_val(__pa(pmdp)) | PMD_TYPE_TABLE)
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#define kvm_mk_p4d(pmdp) \
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__p4d(__phys_to_p4d_val(__pa(pmdp)) | PUD_TYPE_TABLE)
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#define kvm_set_pud(pudp, pud) set_pud(pudp, pud)
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#define kvm_pfn_pte(pfn, prot) pfn_pte(pfn, prot)
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#define kvm_pfn_pmd(pfn, prot) pfn_pmd(pfn, prot)
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#define kvm_pfn_pud(pfn, prot) pfn_pud(pfn, prot)
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#define kvm_pud_pfn(pud) pud_pfn(pud)
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#define kvm_pmd_mkhuge(pmd) pmd_mkhuge(pmd)
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#define kvm_pud_mkhuge(pud) pud_mkhuge(pud)
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static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= PTE_S2_RDWR;
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return pte;
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}
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static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
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{
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pmd_val(pmd) |= PMD_S2_RDWR;
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return pmd;
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}
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static inline pud_t kvm_s2pud_mkwrite(pud_t pud)
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{
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pud_val(pud) |= PUD_S2_RDWR;
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return pud;
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}
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static inline pte_t kvm_s2pte_mkexec(pte_t pte)
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{
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pte_val(pte) &= ~PTE_S2_XN;
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return pte;
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}
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static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
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{
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pmd_val(pmd) &= ~PMD_S2_XN;
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return pmd;
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}
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static inline pud_t kvm_s2pud_mkexec(pud_t pud)
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{
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pud_val(pud) &= ~PUD_S2_XN;
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return pud;
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}
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static inline void kvm_set_s2pte_readonly(pte_t *ptep)
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{
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pteval_t old_pteval, pteval;
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pteval = READ_ONCE(pte_val(*ptep));
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do {
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old_pteval = pteval;
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pteval &= ~PTE_S2_RDWR;
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pteval |= PTE_S2_RDONLY;
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pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
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} while (pteval != old_pteval);
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}
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static inline bool kvm_s2pte_readonly(pte_t *ptep)
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{
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return (READ_ONCE(pte_val(*ptep)) & PTE_S2_RDWR) == PTE_S2_RDONLY;
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}
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static inline bool kvm_s2pte_exec(pte_t *ptep)
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{
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return !(READ_ONCE(pte_val(*ptep)) & PTE_S2_XN);
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}
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static inline void kvm_set_s2pmd_readonly(pmd_t *pmdp)
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{
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kvm_set_s2pte_readonly((pte_t *)pmdp);
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}
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static inline bool kvm_s2pmd_readonly(pmd_t *pmdp)
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{
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return kvm_s2pte_readonly((pte_t *)pmdp);
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}
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static inline bool kvm_s2pmd_exec(pmd_t *pmdp)
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{
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return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN);
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}
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static inline void kvm_set_s2pud_readonly(pud_t *pudp)
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{
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kvm_set_s2pte_readonly((pte_t *)pudp);
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}
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static inline bool kvm_s2pud_readonly(pud_t *pudp)
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{
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return kvm_s2pte_readonly((pte_t *)pudp);
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}
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static inline bool kvm_s2pud_exec(pud_t *pudp)
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{
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return !(READ_ONCE(pud_val(*pudp)) & PUD_S2_XN);
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}
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static inline pud_t kvm_s2pud_mkyoung(pud_t pud)
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{
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return pud_mkyoung(pud);
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}
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static inline bool kvm_s2pud_young(pud_t pud)
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{
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return pud_young(pud);
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}
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#define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
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#ifdef __PAGETABLE_PMD_FOLDED
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#define hyp_pmd_table_empty(pmdp) (0)
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#else
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#define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
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#endif
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#ifdef __PAGETABLE_PUD_FOLDED
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#define hyp_pud_table_empty(pudp) (0)
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#else
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#define hyp_pud_table_empty(pudp) kvm_page_empty(pudp)
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#endif
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#ifdef __PAGETABLE_P4D_FOLDED
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#define hyp_p4d_table_empty(p4dp) (0)
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#else
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#define hyp_p4d_table_empty(p4dp) kvm_page_empty(p4dp)
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#endif
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struct kvm;
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#define kvm_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
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{
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return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
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}
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static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
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{
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void *va = page_address(pfn_to_page(pfn));
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/*
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* With FWB, we ensure that the guest always accesses memory using
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* cacheable attributes, and we don't have to clean to PoC when
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* faulting in pages. Furthermore, FWB implies IDC, so cleaning to
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* PoU is not required either in this case.
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*/
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
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return;
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kvm_flush_dcache_to_poc(va, size);
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}
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static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn,
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unsigned long size)
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{
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if (icache_is_aliasing()) {
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/* any kind of VIPT cache */
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__flush_icache_all();
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} else if (is_kernel_in_hyp_mode() || !icache_is_vpipt()) {
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/* PIPT or VPIPT at EL2 (see comment in __kvm_tlb_flush_vmid_ipa) */
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void *va = page_address(pfn_to_page(pfn));
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invalidate_icache_range((unsigned long)va,
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(unsigned long)va + size);
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}
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}
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static inline void __kvm_flush_dcache_pte(pte_t pte)
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{
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if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
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struct page *page = pte_page(pte);
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kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
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}
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}
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static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
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{
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if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
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struct page *page = pmd_page(pmd);
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kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
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}
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}
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static inline void __kvm_flush_dcache_pud(pud_t pud)
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{
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if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
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struct page *page = pud_page(pud);
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kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
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}
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}
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void kvm_set_way_flush(struct kvm_vcpu *vcpu);
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void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
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static inline bool __kvm_cpu_uses_extended_idmap(void)
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{
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return __cpu_uses_extended_idmap_level();
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}
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static inline unsigned long __kvm_idmap_ptrs_per_pgd(void)
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{
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return idmap_ptrs_per_pgd;
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}
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/*
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* Can't use pgd_populate here, because the extended idmap adds an extra level
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* above CONFIG_PGTABLE_LEVELS (which is 2 or 3 if we're using the extended
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* idmap), and pgd_populate is only available if CONFIG_PGTABLE_LEVELS = 4.
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*/
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static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
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pgd_t *hyp_pgd,
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pgd_t *merged_hyp_pgd,
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unsigned long hyp_idmap_start)
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{
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int idmap_idx;
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u64 pgd_addr;
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/*
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* Use the first entry to access the HYP mappings. It is
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* guaranteed to be free, otherwise we wouldn't use an
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* extended idmap.
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*/
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VM_BUG_ON(pgd_val(merged_hyp_pgd[0]));
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pgd_addr = __phys_to_pgd_val(__pa(hyp_pgd));
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merged_hyp_pgd[0] = __pgd(pgd_addr | PMD_TYPE_TABLE);
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/*
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* Create another extended level entry that points to the boot HYP map,
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* which contains an ID mapping of the HYP init code. We essentially
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* merge the boot and runtime HYP maps by doing so, but they don't
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* overlap anyway, so this is fine.
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*/
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idmap_idx = hyp_idmap_start >> VA_BITS;
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VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx]));
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pgd_addr = __phys_to_pgd_val(__pa(boot_hyp_pgd));
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merged_hyp_pgd[idmap_idx] = __pgd(pgd_addr | PMD_TYPE_TABLE);
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}
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static inline unsigned int kvm_get_vmid_bits(void)
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{
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int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
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return get_vmid_bits(reg);
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}
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/*
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* We are not in the kvm->srcu critical section most of the time, so we take
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* the SRCU read lock here. Since we copy the data from the user page, we
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* can immediately drop the lock again.
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*/
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static inline int kvm_read_guest_lock(struct kvm *kvm,
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gpa_t gpa, void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_read_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
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const void *data, unsigned long len)
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{
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int srcu_idx = srcu_read_lock(&kvm->srcu);
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int ret = kvm_write_guest(kvm, gpa, data, len);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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return ret;
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}
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/*
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* EL2 vectors can be mapped and rerouted in a number of ways,
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* depending on the kernel configuration and CPU present:
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*
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* - If the CPU is affected by Spectre-v2, the hardening sequence is
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* placed in one of the vector slots, which is executed before jumping
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* to the real vectors.
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*
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* - If the CPU also has the ARM64_HARDEN_EL2_VECTORS cap, the slot
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* containing the hardening sequence is mapped next to the idmap page,
|
|
* and executed before jumping to the real vectors.
|
|
*
|
|
* - If the CPU only has the ARM64_HARDEN_EL2_VECTORS cap, then an
|
|
* empty slot is selected, mapped next to the idmap page, and
|
|
* executed before jumping to the real vectors.
|
|
*
|
|
* Note that ARM64_HARDEN_EL2_VECTORS is somewhat incompatible with
|
|
* VHE, as we don't have hypervisor-specific mappings. If the system
|
|
* is VHE and yet selects this capability, it will be ignored.
|
|
*/
|
|
extern void *__kvm_bp_vect_base;
|
|
extern int __kvm_harden_el2_vector_slot;
|
|
|
|
static inline void *kvm_get_hyp_vector(void)
|
|
{
|
|
struct bp_hardening_data *data = arm64_get_bp_hardening_data();
|
|
void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector));
|
|
int slot = -1;
|
|
|
|
if (cpus_have_const_cap(ARM64_SPECTRE_V2) && data->fn) {
|
|
vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs));
|
|
slot = data->hyp_vectors_slot;
|
|
}
|
|
|
|
if (this_cpu_has_cap(ARM64_HARDEN_EL2_VECTORS) && !has_vhe()) {
|
|
vect = __kvm_bp_vect_base;
|
|
if (slot == -1)
|
|
slot = __kvm_harden_el2_vector_slot;
|
|
}
|
|
|
|
if (slot != -1)
|
|
vect += slot * SZ_2K;
|
|
|
|
return vect;
|
|
}
|
|
|
|
#define kvm_phys_to_vttbr(addr) phys_to_ttbr(addr)
|
|
|
|
/*
|
|
* Get the magic number 'x' for VTTBR:BADDR of this KVM instance.
|
|
* With v8.2 LVA extensions, 'x' should be a minimum of 6 with
|
|
* 52bit IPS.
|
|
*/
|
|
static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels)
|
|
{
|
|
int x = ARM64_VTTBR_X(ipa_shift, levels);
|
|
|
|
return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x;
|
|
}
|
|
|
|
static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels)
|
|
{
|
|
unsigned int x = arm64_vttbr_x(ipa_shift, levels);
|
|
|
|
return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x);
|
|
}
|
|
|
|
static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm)
|
|
{
|
|
return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm));
|
|
}
|
|
|
|
static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)
|
|
{
|
|
struct kvm_vmid *vmid = &mmu->vmid;
|
|
u64 vmid_field, baddr;
|
|
u64 cnp = system_supports_cnp() ? VTTBR_CNP_BIT : 0;
|
|
|
|
baddr = mmu->pgd_phys;
|
|
vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
|
|
return kvm_phys_to_vttbr(baddr) | vmid_field | cnp;
|
|
}
|
|
|
|
/*
|
|
* Must be called from hyp code running at EL2 with an updated VTTBR
|
|
* and interrupts disabled.
|
|
*/
|
|
static __always_inline void __load_guest_stage2(struct kvm_s2_mmu *mmu)
|
|
{
|
|
write_sysreg(kern_hyp_va(mmu->kvm)->arch.vtcr, vtcr_el2);
|
|
write_sysreg(kvm_get_vttbr(mmu), vttbr_el2);
|
|
|
|
/*
|
|
* ARM errata 1165522 and 1530923 require the actual execution of the
|
|
* above before we can switch to the EL1/EL0 translation regime used by
|
|
* the guest.
|
|
*/
|
|
asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
|
|
}
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __ARM64_KVM_MMU_H__ */
|