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Robert Jarzmik reports that his PXA25x system fails to boot with 4.12, failing at __flush_whole_cache in arch/arm/mm/proc-xscale.S:215: 0xc0019e20 <+0>: ldr r1, [pc, #788] 0xc0019e24 <+4>: ldr r0, [r1] <== here with r1 containing 0xc06f82cd, which is the address of "clean_addr". Examination of the System.map shows: c06f22c8 D user_pmd_table c06f22cc d __warned.19178 c06f22cd d clean_addr indicating that a .data.unlikely section has appeared just before the .data section from proc-xscale.S. According to objdump -h, it appears that our assembly files default their .data alignment to 2**0, which is bad news if the preceding .data section size is not power-of-2 aligned at link time. Add the appropriate .align directives to all assembly files in arch/arm that are missing them where we require an appropriate alignment. Reported-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
40 lines
962 B
ArmAsm
40 lines
962 B
ArmAsm
/* Bootloader to resume MIO A701
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*
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* 2007-1-12 Robert Jarzmik
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*
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* This code is licenced under the GPLv2.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Note: Yes, part of the following code is located into the .data section.
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* This is to allow jumpaddr to be accessed with a relative load
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* while we can't rely on any MMU translation. We could have put
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* sleep_save_sp in the .text section as well, but some setups might
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* insist on it to be truly read-only.
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*/
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.data
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.align 2
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ENTRY(mioa701_bootstrap)
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0:
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b 1f
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ENTRY(mioa701_jumpaddr)
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.word 0x40f00008 @ PSPR in no-MMU mode
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1:
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mov r0, #0xa0000000 @ Don't suppose memory access works
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orr r0, r0, #0x00200000 @ even if it's supposed to
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orr r0, r0, #0x0000b000
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mov r1, #0
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str r1, [r0] @ Early disable resume for next boot
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ldr r0, mioa701_jumpaddr @ (Murphy's Law)
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ldr r0, [r0]
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ret r0
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2:
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ENTRY(mioa701_bootstrap_lg)
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.data
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.align 2
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.word 2b-0b
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