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152d32aa84
- Stage-2 isolation for the host kernel when running in protected mode - Guest SVE support when running in nVHE mode - Force W^X hypervisor mappings in nVHE mode - ITS save/restore for guests using direct injection with GICv4.1 - nVHE panics now produce readable backtraces - Guest support for PTP using the ptp_kvm driver - Performance improvements in the S2 fault handler x86: - Optimizations and cleanup of nested SVM code - AMD: Support for virtual SPEC_CTRL - Optimizations of the new MMU code: fast invalidation, zap under read lock, enable/disably dirty page logging under read lock - /dev/kvm API for AMD SEV live migration (guest API coming soon) - support SEV virtual machines sharing the same encryption context - support SGX in virtual machines - add a few more statistics - improved directed yield heuristics - Lots and lots of cleanups Generic: - Rework of MMU notifier interface, simplifying and optimizing the architecture-specific code - Some selftests improvements -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmCJ13kUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroM1HAgAqzPxEtiTPTFeFJV5cnPPJ3dFoFDK y/juZJUQ1AOtvuWzzwuf175ewkv9vfmtG6rVohpNSkUlJYeoc6tw7n8BTTzCVC1b c/4Dnrjeycr6cskYlzaPyV6MSgjSv5gfyj1LA5UEM16LDyekmaynosVWY5wJhju+ Bnyid8l8Utgz+TLLYogfQJQECCrsU0Wm//n+8TWQgLf1uuiwshU5JJe7b43diJrY +2DX+8p9yWXCTz62sCeDWNahUv8AbXpMeJ8uqZPYcN1P0gSEUGu8xKmLOFf9kR7b M4U1Gyz8QQbjd2lqnwiWIkvRLX6gyGVbq2zH0QbhUe5gg3qGUX7JjrhdDQ== =AXUi -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm updates from Paolo Bonzini: "This is a large update by KVM standards, including AMD PSP (Platform Security Processor, aka "AMD Secure Technology") and ARM CoreSight (debug and trace) changes. ARM: - CoreSight: Add support for ETE and TRBE - Stage-2 isolation for the host kernel when running in protected mode - Guest SVE support when running in nVHE mode - Force W^X hypervisor mappings in nVHE mode - ITS save/restore for guests using direct injection with GICv4.1 - nVHE panics now produce readable backtraces - Guest support for PTP using the ptp_kvm driver - Performance improvements in the S2 fault handler x86: - AMD PSP driver changes - Optimizations and cleanup of nested SVM code - AMD: Support for virtual SPEC_CTRL - Optimizations of the new MMU code: fast invalidation, zap under read lock, enable/disably dirty page logging under read lock - /dev/kvm API for AMD SEV live migration (guest API coming soon) - support SEV virtual machines sharing the same encryption context - support SGX in virtual machines - add a few more statistics - improved directed yield heuristics - Lots and lots of cleanups Generic: - Rework of MMU notifier interface, simplifying and optimizing the architecture-specific code - a handful of "Get rid of oprofile leftovers" patches - Some selftests improvements" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (379 commits) KVM: selftests: Speed up set_memory_region_test selftests: kvm: Fix the check of return value KVM: x86: Take advantage of kvm_arch_dy_has_pending_interrupt() KVM: SVM: Skip SEV cache flush if no ASIDs have been used KVM: SVM: Remove an unnecessary prototype declaration of sev_flush_asids() KVM: SVM: Drop redundant svm_sev_enabled() helper KVM: SVM: Move SEV VMCB tracking allocation to sev.c KVM: SVM: Explicitly check max SEV ASID during sev_hardware_setup() KVM: SVM: Unconditionally invoke sev_hardware_teardown() KVM: SVM: Enable SEV/SEV-ES functionality by default (when supported) KVM: SVM: Condition sev_enabled and sev_es_enabled on CONFIG_KVM_AMD_SEV=y KVM: SVM: Append "_enabled" to module-scoped SEV/SEV-ES control variables KVM: SEV: Mask CPUID[0x8000001F].eax according to supported features KVM: SVM: Move SEV module params/variables to sev.c KVM: SVM: Disable SEV/SEV-ES if NPT is disabled KVM: SVM: Free sev_asid_bitmap during init if SEV setup fails KVM: SVM: Zero out the VMCB array used to track SEV ASID association x86/sev: Drop redundant and potentially misleading 'sev_enabled' KVM: x86: Move reverse CPUID helpers to separate header file KVM: x86: Rename GPR accessors to make mode-aware variants the defaults ...
169 lines
5.0 KiB
C
169 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_MMU_INTERNAL_H
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#define __KVM_X86_MMU_INTERNAL_H
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_host.h>
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#undef MMU_DEBUG
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#ifdef MMU_DEBUG
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extern bool dbg;
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#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
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#define rmap_printk(fmt, args...) do { if (dbg) printk("%s: " fmt, __func__, ## args); } while (0)
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#define MMU_WARN_ON(x) WARN_ON(x)
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#else
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#define pgprintk(x...) do { } while (0)
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#define rmap_printk(x...) do { } while (0)
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#define MMU_WARN_ON(x) do { } while (0)
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#endif
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/*
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* Unlike regular MMU roots, PAE "roots", a.k.a. PDPTEs/PDPTRs, have a PRESENT
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* bit, and thus are guaranteed to be non-zero when valid. And, when a guest
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* PDPTR is !PRESENT, its corresponding PAE root cannot be set to INVALID_PAGE,
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* as the CPU would treat that as PRESENT PDPTR with reserved bits set. Use
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* '0' instead of INVALID_PAGE to indicate an invalid PAE root.
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*/
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#define INVALID_PAE_ROOT 0
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#define IS_VALID_PAE_ROOT(x) (!!(x))
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struct kvm_mmu_page {
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struct list_head link;
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struct hlist_node hash_link;
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struct list_head lpage_disallowed_link;
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bool unsync;
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u8 mmu_valid_gen;
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bool mmio_cached;
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bool lpage_disallowed; /* Can't be replaced by an equiv large page */
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/*
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* The following two entries are used to key the shadow page in the
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* hash table.
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*/
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union kvm_mmu_page_role role;
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gfn_t gfn;
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u64 *spt;
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/* hold the gfn of each spte inside spt */
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gfn_t *gfns;
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/* Currently serving as active root */
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union {
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int root_count;
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refcount_t tdp_mmu_root_count;
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};
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unsigned int unsync_children;
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struct kvm_rmap_head parent_ptes; /* rmap pointers to parent sptes */
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DECLARE_BITMAP(unsync_child_bitmap, 512);
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#ifdef CONFIG_X86_32
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/*
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* Used out of the mmu-lock to avoid reading spte values while an
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* update is in progress; see the comments in __get_spte_lockless().
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*/
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int clear_spte_count;
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#endif
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/* Number of writes since the last time traversal visited this page. */
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atomic_t write_flooding_count;
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#ifdef CONFIG_X86_64
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bool tdp_mmu_page;
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/* Used for freeing the page asynchronously if it is a TDP MMU page. */
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struct rcu_head rcu_head;
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#endif
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};
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extern struct kmem_cache *mmu_page_header_cache;
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static inline struct kvm_mmu_page *to_shadow_page(hpa_t shadow_page)
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{
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struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
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return (struct kvm_mmu_page *)page_private(page);
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}
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static inline struct kvm_mmu_page *sptep_to_sp(u64 *sptep)
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{
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return to_shadow_page(__pa(sptep));
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}
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static inline int kvm_mmu_role_as_id(union kvm_mmu_page_role role)
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{
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return role.smm ? 1 : 0;
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}
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static inline int kvm_mmu_page_as_id(struct kvm_mmu_page *sp)
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{
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return kvm_mmu_role_as_id(sp->role);
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}
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static inline bool kvm_vcpu_ad_need_write_protect(struct kvm_vcpu *vcpu)
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{
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/*
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* When using the EPT page-modification log, the GPAs in the CPU dirty
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* log would come from L2 rather than L1. Therefore, we need to rely
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* on write protection to record dirty pages, which bypasses PML, since
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* writes now result in a vmexit. Note, the check on CPU dirty logging
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* being enabled is mandatory as the bits used to denote WP-only SPTEs
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* are reserved for NPT w/ PAE (32-bit KVM).
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*/
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return vcpu->arch.mmu == &vcpu->arch.guest_mmu &&
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kvm_x86_ops.cpu_dirty_log_size;
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}
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bool is_nx_huge_page_enabled(void);
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bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
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bool can_unsync);
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void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn);
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bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
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struct kvm_memory_slot *slot, u64 gfn);
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void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
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u64 start_gfn, u64 pages);
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/*
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* Return values of handle_mmio_page_fault, mmu.page_fault, and fast_page_fault().
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*
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* RET_PF_RETRY: let CPU fault again on the address.
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* RET_PF_EMULATE: mmio page fault, emulate the instruction directly.
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* RET_PF_INVALID: the spte is invalid, let the real page fault path update it.
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* RET_PF_FIXED: The faulting entry has been fixed.
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* RET_PF_SPURIOUS: The faulting entry was already fixed, e.g. by another vCPU.
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*/
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enum {
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RET_PF_RETRY = 0,
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RET_PF_EMULATE,
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RET_PF_INVALID,
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RET_PF_FIXED,
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RET_PF_SPURIOUS,
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};
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/* Bits which may be returned by set_spte() */
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#define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
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#define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
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#define SET_SPTE_SPURIOUS BIT(2)
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int kvm_mmu_max_mapping_level(struct kvm *kvm,
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const struct kvm_memory_slot *slot, gfn_t gfn,
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kvm_pfn_t pfn, int max_level);
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int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
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int max_level, kvm_pfn_t *pfnp,
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bool huge_page_disallowed, int *req_level);
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void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
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kvm_pfn_t *pfnp, int *goal_levelp);
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bool is_nx_huge_page_enabled(void);
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void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc);
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void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp);
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void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp);
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#endif /* __KVM_X86_MMU_INTERNAL_H */
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